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iCE40HX-8K Breakout Board
Evaluation Board User Guide
DNI
DNI
DNI
DNI
+3.3V
TP4
TP4
TP5
TP5
R21
R21
1
1
D
C
B
A
14
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5
VCCIO0
U3A
U3A
iCE40HX8K-CT256
iCE40HX8K-CT256
A13
VCCIO0_01
A3
VCCIO0_02
C14
C14
C17
C17
C18
C18
C15
C15
A8
VCCIO0_03
F8
VCCIO0_04
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
DNI
DNI
DNI
DNI
+1.2V
TP6
TP6
TP7
TP7
R23
R23
E8
PLLVCC0
E7
PLLGND_0
100
100
C22
C22
C23
C23
10uF
10uF
0.1uF
0.1uF
F7
GBIN0/PIO0_26
C8
GBIN1/PIO0_25
VCCIO0
C25
C25
0.1uF
0.1uF
PIO0_01
PIO0_03
PIO0_15
PIO0_14
PIO0_20
PIO0_27
PIO0_30
PIO0_31
PIO0_34
PIO0_45
PIO0_46
PIO0_51
PIO0_47
PIO0_44
5
© 2013-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal.
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4
C14
PIO0_00
B15
PIO0_01
DCDn
PIO0_01
D13
PIO0_02
B14
PIO0_03
DSRn
PIO0_03
C12
PIO0_04
E11
PIO0_05
C13
PIO0_06
A16
PIO0_07
DTRn
PIO0_07
A15
PIO0_08
CTSn
PIO0_08
B13
PIO0_09
RTSn
PIO0_09
E10
PIO0_10
C11
PIO0_11
D11
PIO0_12
B12
PIO0_13
RS232_Tx_TTL
PIO0_13
B10
PIO0_14
RS232_Rx_TTL
PIO0_14
B11
PIO0_15
PIO0_15
C10
PIO0_16
A10
PIO0_17
PIO0_17
A11
PIO0_18
PIO0_18
D10
PIO0_19
C9
PIO0_20
PIO0_20
E9
PIO0_21
D9
PIO0_22
A9
PIO0_23
PIO0_23
F9
PIO0_24
B9
PIO0_27
PIO0_27
BANK0
BANK0
D8
PIO0_28
B8
PIO0_29
PIO0_29
A7
PIO0_30
PIO0_30
C7
PIO0_31
PIO0_31
B7
PIO0_32
PIO0_32
B6
PIO0_33
PIO0_33
C6
PIO0_34
PIO0_34
D7
PIO0_35
A6
PIO0_36
PIO0_36
D6
PIO0_37
A5
PIO0_38
PIO0_38
B5
PIO0_39
LED0
PIO0_39
E6
PIO0_40
B4
PIO0_41
LED1
PIO0_41
A2
PIO0_42
LED2
PIO0_42
D5
PIO0_43
A1
PIO0_44
LED3
PIO0_44
C5
PIO0_45
LED4
PIO0_45
C4
PIO0_46
LED5
PIO0_46
B3
PIO0_47
LED6
PIO0_47
D4
PIO0_48
E5
PIO0_49
D3
PIO0_50
C3
PIO0_51
LED7
PIO0_51
MAKE PWR TRACES
CAPABLE OF 1A
J1
J1
2
1
PIO0_07
4
3
PIO0_08
6
5
PIO0_09
8
7
10
9
PIO0_13
12
11
PIO0_18
14
13
PIO0_17
16
15
18
17
PIO0_23
20
19
PIO0_29
22
21
PIO0_32
24
23
26
25
PIO0_36
28
27
PIO0_33
30
29
PIO0_38
32
31
34
33
PIO0_39
36
35
PIO0_41
38
37
PIO0_42
40
39
Header2x20
Header2x20
DNI
DNI
4
Figure A.3. FPGA
3
DNI
DNI
DNI
DNI
+3.3V
VCCIO1
TP8
TP8
TP9
TP9
R22
R22
2
1
1
C21
C21
2
0.1uF
0.1uF
2
2
2
2
2
5
5
5
5
5
5
5
5
VCCIO1
VCC_1.2V
MAKE PWR TRACES
CAPABLE OF 1A
C24
C24
J2
J2
0.1uF
0.1uF
2
1
4
3
PIO1_01
PIO1_03
6
5
8
7
PIO1_14
10
9
PIO1_16
12
11
PIO1_21
14
13
16
15
PIO1_22
18
17
PIO1_42
20
19
PIO1_29
22
21
24
23
PIO1_32
26
25
PIO1_36
28
27
PIO1_46
30
29
32
31
PIO1_44
34
33
PIO1_51
36
35
PIO1_49
38
37
40
39
Header2x20
Header2x20
3
2
U3B
U3B
iCE40HX8K-CT256
iCE40HX8K-CT256
H10
VCCIO1_01
PI
C15
VCCIO1_02
PI
C19
C19
C16
C16
C20
C20
H15
VCCIO1_03
PI
N15
VCCIO1_04
PI
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
PI
PI
PI
PI
PI
PI
PI
PI
R14
PIO1_00
PI
PIO1_01
R15
PIO1_01
PI
P14
PIO1_02
PI
PIO1_03
P15
PIO1_03
PI
N14
TRST_B
PI
PI
PI
R24
R24
PI
PI
10K
10K
PI
PI
BANK1
BANK1
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
PI
GBIN2/PIO1_28
H16
GBIN2/PIO1_28
PI
H11
GBIN3/PIO1_27
PI
C26
C26
C27
C27
0.1uF
0.1uF
0.1uF
0.1uF
PIO1_04
PIO1_08
PIO1_12
PIO1_20
PIO1_18
PIO1_37
PIO1_19
GBIN2/PIO1_28
PIO1_30
PIO1_34
PIO1_38
PIO1_40
PIO1_47
AXELSYS
AXELSYS
AXELSYS
Title
Title
Title
iCE40-HX8K B
iCE40-HX8K B
iCE40-HX8K B
S
S
S
z i
z i
z i
e
e
e
D
D
D
o
o
o
c
c
c
u
u
u
m
m
m
e
e
e
t n
t n
t n
N
N
N
u
u
u
m
m
m
b
b
b
r e
r e
r e
B
B
B
ICE40HX8K-B-EV
ICE40HX8K-B-EV
ICE40HX8K-B-EV
D
D
D
t a
t a
t a
: e
: e
: e
Jul 27, 2013
Jul 27, 2013
Jul 27, 2013
2
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