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Lattice Semiconductor
Table 12. SERDES to SATA Connections
CN1 Pin
1
2
3
A_HDOUTN1_R
4
5
6
7
SERDES PCI Express Channels
(see Appendix A, Figure 8)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edge-
fingers (CN1) to fit directly into an x1 host receptacle. Power can be supplied directly from the PCI Express host via
the edge-finger connections.
Table 13. SERDES to PCI Express Connections
PCI Express
Pin
B14
B15
A16
A17
A13
A14
FPGA Test Pins
(see Appendix A, Figure 15)
General purpose FPGA pins are available for user applications. FPGA pins are connected to SW4 DIP switch. This
switch is used for static settings to FPGA input pins. The pins must be set to LVCMOS18 buffer types and are exter-
nally pulled up when the switch is open and driven low when the switch is set to "ON" or closed.
General purpose outputs are connected to LEDs for observing output status of pins. The FPGA output buffers
should be LVCMOS18 and will illuminate the LED when driving a "1" and the LED will be off when driving a "0" or
when not used.
Table 14. FPGA Test Pins (see Appendix A, Figure 15)
Switch
SW4A
SW4B
SW4C
SW4D
SW4E
SW4F
SW4G
SW4H
900-Ball
SERDES Pin
fpBGA
__
GND
A_HDOUTP1_R
A25
A26
__
GND
A_HDINP1_R
B25
A_HDINN1_R
B26
__
GND
PCI Express
Signal
PETp0
PETn0
PERp0
PERn0
Refclk+
Refclk-
BGA
Netname
G28
Switch1
F28
Switch2
L25
Switch3
L26
Switch4
E29
Switch5
E30
Switch6
J28
Switch7
H28
Switch8
Evaluation Board User's Guide
CN2 Pin
1
2
3
4
5
6
7
SCM Device Pin
A_HDINP0_L
A_HDINN0_L
A_HDOUTP0_L
A_HDOUTN0_L
FPGA URC_A PLL Input+
FPGA URC_A PLL Input+
LED
900-Ball fpBGA
D15
H26
D16
G26
D17
D29
D18
D30
D19
K25
D20
K26
D21
H30
D22
K30
11
LatticeSC PCI Express x1
900-Ball
SERDES Pin
fpBGA
__
GND
A_HDINP2_R
B24
A_HDINN2_R
B23
__
GND
A_HDOUTP2_R
A24
A_HDOUTN2_R
A23
__
GND
900-Ball
fpBGA
B3
B4
A3
A4
D28
E28
NetName
LED Color
LED1
Red
LED2
Yellow
LED3
Green
LED4
Blue
LED5
Red
LED6
Yellow
LED7
Green
LED8
Blue
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