I/O Voltage Rails - Xilinx ML605 User Manual

Chapter 1: ML605 Evaluation Board
The ML605 supports Master BPI-Up, JTAG, and Slave SelectMAP. These are selected by
setting M[2:0] options 010, 101 and 110 shown in
Table 1-2: Virtex-6 FPGA Configuration Modes
Notes:
1. The parallel configuration modes bus is auto-detected by the configuration logic.
2. In Master configuration mode, the CCLK pin is the clock source for the Virtex-6 FPGA internal
3. This is the default setting due to internal pull-up termination on mode pins.
For an overview on configuring the FPGA, see
Note:
page
be OFF to disable the System ACE controller from attempting to boot if a CF card is present.
References
See the Virtex-6 FPGA Configuration User Guide for detailed configuration information.
[Ref 5]

I/O Voltage Rails

There are 16 I/O banks available on the Virtex-6 device. The voltage applied to the FPGA
I/O banks used by the ML605 board is summarized in
Table 1-3: Voltage Rails
14
Configuration Mode
(2)
Master Serial
(2)
Master SPI
(2)
Master BPI-Up
(2)
Master BPI-Down
(2)
Master SelectMAP
JTAG
Slave SelectMAP
(3)
Slave Serial
configuration logic. The Virtex-6 FPGA CCLK output pin must be free from reflections to avoid
double-clocking the internal configuration logic. See the Virtex-6 FPGA Configuration User Guide for
more details. [Ref 5]
The mode switches are part of DIP switch S2. The default mode setting (see
75) is M[2:0]=010, which selects Master BPI-Up at board power-on. Switch S1 position 4 must
U1 FPGA Bank
Bank 0 VCC2V5_FPGA
(1)
Bank 12 FMC_VIO_B_M2C
Bank 13 VCC2V5_FPGA
Bank 14 VCC2V5_FPGA
Bank 15 VCC2V5_FPGA
Bank 16 VCC2V5_FPGA
Bank 22 VCC2V5_FPGA
Bank 23 VCC2V5_FPGA
www.xilinx.com
Table
M[2:0] Bus Width
000
001
8, 16
010
8, 16
011
8, 16
100
101
8, 16, 32
110
111
"Configuration Options," page
Table
I/O Rail Voltage
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
2.5V
1-2.
(1)
CCLK Direction
1 Output
1 Output
Output
Output
Output
1 Input (TCK)
Input
1 Input
73.
Table A-1,
1-3.
ML605 Hardware User Guide
UG534 (v1.2.1) January 21, 2010