Ethernet Packet Generator Control 2; Table 3.35 Epg Control Register 2, Address 30E1 (0X1E) - Renesas R-IN32M4-CL2 User Manual

R-IN32M4-CL2 User's Manual Gigabit Ethernet PHY Edition
3.3.5

Ethernet Packet Generator Control 2

Register 30E1 consists of the second set of bits that provide access to and control over the various aspects of the EPG
testing feature. The following table shows the settings available.

Table 3.35 EPG Control Register 2, Address 30E1 (0x1E)

Bit Name
15:0 EPG packet payload
Caution: If any of bits 15:0 in this register are changed while the EPG is running (bit 14 of register 29E1 is set to 1), that bit
(29E1.14) must first be cleared and then set back to 1 for the change to take effect and to restart the EPG.
R18UZ0043EJ0100
Mar 4, 2016
Access
R/W Data pattern repeated in the payload of packets generated by
the EPG
Description
3. Registers
Default
0x0000
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