Mode Control; Table 3.3 Mode Control, Address 0 (0X00) - Renesas R-IN32M4-CL2 User Manual

R-IN32M4-CL2 User's Manual Gigabit Ethernet PHY Edition
3.2.1

Mode Control

The device register at memory address 0 controls several aspects of the GbE-PHY functionality. The following table
shows the available bit settings in this register and what they control.

Table 3.3 Mode Control, Address 0 (0x00)

Bit Name
15 Software reset
14 Loopback
13 Forced speed selection LSB
12 Autonegotiation enable
11 Power-down
10 Isolate
9 Restart autonegotiation
8 Duplex
7 Collision test enable
6 Forced speed selection MSB
5:0 Reserved
Note: Before selecting the 1000 Mbps forced speed mode, manually configure the PHY as master or slave by setting bit
11 in register 9 (1000BASE-T Control). Each time the link drops, the PHY needs to be powered down(0.11)
manually to enable it to link up again using the master/slave setting specified in register 9.11.
R18UZ0043EJ0100
Mar 4, 2016
Access
R/W Self-clearing. Restores all serial management interface (SMI)
registers to default state, except for sticky and super-sticky bits.
1: Reset asserted.
0: Reset de-asserted.
Wait 1us after setting this bit to initiate another SMI register
access.
R/W 1: Loopback enabled.
0: Loopback disabled.
When loop back is enabled, the device functions at the current
speed setting and with the current duplex mode setting (bits 6, 8,
and 13 of this register).
Note
R/W
Bit6
0
0
1
1
R/W 1: Autonegotiation enabled.
0: Autonegotiation disabled.
R/W 1: Power-down enabled.
R/W 1: Disable MAC interface outputs and ignore MAC interface
inputs.
R/W Self-clearing bit.
1: Restart autonegotiation on media interface.
R/W 1: Full-duplex.
0: Half-duplex.
R/W 1: Collision test enabled.
Note
R/W
Bit6
0
0
1
1
RO Reserved.
Description
Bit1 Communication speed
0 10 Mbps.
1 100 Mbps.
0 1000 Mbps. (Initial Value)
1 Setting prohibited
Bit13 Communication speed
0 10 Mbps.
1 100 Mbps.
0 1000 Mbps. (Initial Value)
1 Setting prohibited
3. Registers
Default
0
0
0
1
0
0
0
0
0
1
0x00
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