Mode Status; Device Identification; Table 3.4 Mode Status, Address 1 (0X01); Table 3.5 Phy Identifier 1, Address 2 (0X02) - Renesas R-IN32M4-CL2 User Manual

Gigabit ethernet phy edition
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R-IN32M4-CL2 User's Manual Gigabit Ethernet PHY Edition
3.2.2

Mode Status

The register at address 1 in the device main registers space enables reading the currently enabled mode setting. The
following table shows possible readouts of this register.

Table 3.4 Mode Status, Address 1 (0x01)

Bit
Name
15
100BASE-T4 capability
14
100BASE-TX FDX capability
13
100BASE-TX HDX capability
12
10BASE-T FDX capability
11
10BASE-T HDX capability
10
100BASE-T2 FDX capability
9
100BASE-T2 HDX capability
8
Extended status enable
7
Reserved
6
Preamble suppression capability
5
Autonegotiation complete
4
Remote fault
3
Autonegotiation capability
2
Link status
1
Jabber detect
0
Extended capability
3.2.3

Device Identification

All 16 bits in both register 2 and register 3 in the GbE-PHY are used to provide information associated with aspects of
the device identification. The following tables list the expected readouts.

Table 3.5 PHY Identifier 1, Address 2 (0x02)

Bit
15:0
Organizationally unique identifier (OUI)

Table 3.6 PHY Identifier 2, Address 3 (0x03)

Bit
15:10 OUI
9:4
Model number
3:0
Device revision number
R18UZ0043EJ0100
Mar 4, 2016
Access
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Name
Name
Description
1: 100BASE-T4 capable.
1: 100BASE-TX FDX capable.
1: 100BASE-TX HDX capable.
1: 10BASE-T FDX capable.
1: 10BASE-T HDX capable.
1: 100BASE-T2 FDX capable.
1: 100BASE-T2 HDX capable.
1: Extended status information present in register 15.
Reserved.
1: MF preamble can be suppressed.
0: MF preamble required.
(MF: Management Frame)
1: Autonegotiation complete.
Latches high.
1: Far-end fault detected.
1: Autonegotiation capable.
Latches low.
1: Link is up.
Latches high.
1: Jabber condition detected.
1: Extended register capable.
Access
RO
OUI most significant bits (3:18)
Access
RO
OUI least significant bits (19:24)
RO
Model number
RO
Revision A
3. Registers
Description
Description
Page 17 of 39
Default
0
1
1
1
1
0
0
1
1
1
0
0
1
0
0
1
Default
0×0007
Default
000001
100011
0001

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