Far-End Loopback; Near-End Loopback; Figure 2.3 Far-End Loopback Diagram; Figure 2.4 Near-End Loopback Diagram - Renesas R-IN32M4-CL2 User Manual

R-IN32M4-CL2 User's Manual Gigabit Ethernet PHY Edition
2.5.2

Far-End Loopback

The far-end loopback testing feature is enabled by setting register bit 23.3 to 1. When enabled, it forces incoming data
from a link partner on the current media interface into the MAC interface of the PHY where it is retransmitted back to the
link partner on the media interface as shown in the following illustration. In addition, the incoming data also appears on
the receive data pins of the MAC interface. Data present on the transmit data pins of the MAC interface is ignored when
using this testing feature.
Link Partner

Figure 2.3 Far-End Loopback Diagram

2.5.3

Near-End Loopback

When the near-end loopback testing feature is enabled, transmitted data (TXD) is looped back in the PCS block onto
the receive data signals (RXD), as shown in the following illustration. When using this testing feature, no data is
transmitted over the network. To enable near-end loopback, set the device register bit 0.14 to 1.
Link Partner

Figure 2.4 Near-End Loopback Diagram

R18UZ0043EJ0100
Mar 4, 2016
RX
PHY_port_n
TX
RX
TX
PHY_port_n
2. Functional Descriptions
RXD
MAC
TXD
RXD
MAC
TXD
Page 11 of 39