Design Considerations - Renesas R-IN32M4-CL2 User Manual

R-IN32M4-CL2 User's Manual Gigabit Ethernet PHY Edition
4.

Design Considerations

This section provides information about design considerations for the GbE-PHY device.
(1) 1000BASE-T distortion
Silicon from some process corners at voltage and temperature extremes may not pass IEEE802.3 1000BASE-T
distortion specification requirement of <10 mV across 60% of UI.
This marginality does not have any real-world link performance impact, and no BER or interoperability issues have
been seen as a result.
(2) 10BASE-T signal amplitude
10BASE-T signal amplitude can be lower than the minimum specified in IEEE 802.3 paragraph 14.3.1.2.1 (2.2 V) if
2.5V is supplied with the low voltage. Additionally, associated templates may be marginal or have failures.
This issue is not estimated to present any system level impact. Performance is not impaired with cables up to 130 m
with various link partners.
(3) 10BASE-T transmitter return loss
10BASE-T transmitter return loss can be 15dB below the incident from the range of 5MHz to 10MHz for each of the
resistances: 100Ω, 85Ω, and 111Ω when using a random data pattern.
This issue is not estimated to present any system level impact. Performance is not impaired with cables up to 130 m
with various link partners.
R18UZ0043EJ0100
Mar 4, 2016
4. Design Considerations
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