Renesas RA Series Quick Design Manual

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Renesas RA Family

RA0 Quick Design Guide

Introduction

This document answers common questions and points out subtleties of the RA0 MCU that might be missed

unless the hardware manual was extensively reviewed. The document is not intended to be a replacement

for the hardware manual. It is intended to supplement the manual by highlighting some key items most

engineers will need to start their own design. It also discusses some design decisions from an application

point of view.

Target Device

RA0 MCU Series

Contents

Power Supplies ........................................................................................................................ 3

1.1

References .............................................................................................................................................. 3

Emulator Support ..................................................................................................................... 4

2.1

SWD Interface ......................................................................................................................................... 4

MCU Operating Modes ............................................................................................................ 5

Option-Setting Memory ............................................................................................................ 6

4.1

Option-Setting Memory Registers ........................................................................................................... 7

Clock Circuits ........................................................................................................................... 8

5.1

Reset Conditions ..................................................................................................................................... 9

5.2

Clock Frequency Requirements .............................................................................................................. 9

5.2.1

Requirements for Programming and Erasing ROM or Data Flash ........................................................ 9

5.3

Lowering Clock Generation Circuit (CGC) Power Consumption ............................................................. 9

5.4

Writing the System Clock Control Registers ......................................................................................... 10

5.5

Clock Setup Example ............................................................................................................................ 10

5.6

HOCO Accuracy .................................................................................................................................... 11

5.7

Flash Interface Clock ............................................................................................................................. 11

5.8

Board Design ......................................................................................................................................... 11

5.9

External Crystal Resonator Selection.................................................................................................... 11

5.10 External Clock Input .............................................................................................................................. 12

Reset Requirements and the Reset Circuit ............................................................................ 12

6.1

Pin Reset ............................................................................................................................................... 12

6.2

Power-On Reset .................................................................................................................................... 13

6.3

Independent Watchdog Timer Reset ..................................................................................................... 13

6.4

Voltage-Monitoring Resets .................................................................................................................... 13

6.5

Software Reset ...................................................................................................................................... 13

R01AN7309EU0100 Rev.1.00

Apr.09.24

Application Note

Page 1 of 33

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Summary of Contents for Renesas RA Series

Page 1: Table Of Contents
Application Note Renesas RA Family RA0 Quick Design Guide Introduction This document answers common questions and points out subtleties of the RA0 MCU that might be missed unless the hardware manual was extensively reviewed. The document is not intended to be a replacement for the hardware manual.
Page 2 Renesas RA Family RA0 Quick Design Guide Other Resets ............................14 Determination of Cold/Warm Start ......................14 Determining the Reset Source ......................14 Memory ..........................15 SRAM ..............................16 Peripheral I/O Registers ........................16 On-Chip Flash Memory ......................... 16 7.3.1 Background Operation ........................
Page 3: Power Supplies
Renesas RA Family RA0 Quick Design Guide 1. Power Supplies The RA0 family has digital power supplies and analog power supplies. The power supplies use the following pins. Table 1. Digital Power Supplies Symbol Name Description Power supply Power supply pin. Connect to the system power supply.
Page 4: Emulator Support
Renesas RA Family RA0 Quick Design Guide 2. Emulator Support RA0 MCU devices have an emulator interface that supports debugging using SWD communication. ® The SWD emulator interface can be connected to an Arm -standard 10-pin or 20-pin socket. ®...
Page 5: Mcu Operating Modes
It is important to note that RA0 MCU devices do not have an MD (Mode) pin. This is different from other Renesas RA devices. RA0 MCU devices do not support SCI Boot Mode, so there is no need for the MD pin.
Page 6: Option-Setting Memory
Renesas RA Family RA0 Quick Design Guide 4. Option-Setting Memory The option-setting memory determines the state of the MCU after a reset. It is allocated to the configuration setting area and the program flash area of the flash memory. The available methods for configuration are different for the two areas.
Page 7: Option-Setting Memory Registers
 Port 206 / RES function selection.  Flash Read Protection after reset. Renesas FSP Configurator supports setting of Option Function Select Registers in BSP settings, as shown in Figure 4 for RA0E1 MCU. Figure 4. Option Function Select Register Settings in FSP Configuration for RA0E1 MCU R01AN7309EU0100 Rev.1.00...
Page 8: Clock Circuits
Renesas RA Family RA0 Quick Design Guide Clock Circuits RA0 MCUs have five primary oscillators. All five of these may be used as the source for the main system clock. In a typical system, the main clock is driven with an external crystal or clock. This input is directed to internal selectors and frequency dividers, where it is further directed to the main system clock (ICLK), flash clock, CPU clock, and peripheral module clocks.
Page 9: Reset Conditions
Renesas RA Family RA0 Quick Design Guide 5.1 Reset Conditions After reset, RA0 MCUs begin running with the high-speed on-chip oscillator (HOCO) as the main clock source. At reset, the main clock oscillator is stopped by default and the pins are set to port mode. The SOSC, LOCO, MOCO, are stopped by default after reset.
Page 10: Writing The System Clock Control Registers
Figure 5. Timing of Clock Source Switching 5.5 Clock Setup Example Renesas FSP provides a simple, visual clock configuration tool for all RA0 MCUs. An example for RA0E1 MCU group is shown below. This configurator configures code in the board support package to initialize the Clock Generation Circuit based on user selection, with proper precautions as indicated in the MCU Hardware User’s Manual.
Page 11: Hoco Accuracy
Renesas RA Family RA0 Quick Design Guide 5.6 HOCO Accuracy The internal high-speed on-chip oscillator (HOCO) runs at 24 MHz or 32 MHz for RA0 devices. Once the HOCO Clock Oscillation Stabilization Flag (HOCOSF) has been set to 1, the HOCO will have a typical accuracy of +/-1% or better.
Page 12: External Clock Input
For more accurate results, also take into account the stray capacitance associated with the routing between the crystal resonator components. The Renesas RA Family Design Guide for Sub-Clock Circuits provides details on board design specification for both the external crystal and sub-clock oscillator.
Page 13: Power-On Reset
Renesas RA Family RA0 Quick Design Guide requirements. Also refer to section 2, Emulator Support for details on reset circuitry in relation to debug support. There is no need to use an external capacitor on the RES line because the POR circuit holds it low internally for a good reset and a minimum reset pulse is required to initiate this process.
Page 14: Other Resets
The following sample code shows how to determine if a reset is caused by Power On Reset or Software Reset using CMSIS based register structure in Renesas FSP. /* Power on Reset */ if(1 == R_SYSTEM->PORSR_b.PORF) /* Do something */ …...
Page 15: Memory
Renesas RA Family RA0 Quick Design Guide 7. Memory The RA0 MCUs support a 4 GB linear address space ranging from 0000 0000h to FFFF FFFFh that can contain program, and data. Program and data memory share the address space. Separate buses are used to access each, increasing performance and allowing same-cycle access of program and data.
Page 16: Sram
Flash I/O registers to control access flash memory occupy the region from 407E 0000h to 407F FFFFh. The Renesas FSP provide C header files in CMSIS data structure that map all of the peripheral I/O registers for a specific device to easily accessible I/O data structures.
Page 17: Background Operation
Renesas RA Family RA0 Quick Design Guide The following figure shows example specifications of code flash memory and data flash memory. Figure 12. Specifications of Code Flash Memory and Data Flash Memory on RA0E1 MCU 7.3.1 Background Operation RA0 MCUs support background operations (BGO) for data flash. This means that when a program or erase starts, the user can keep executing and accessing memory from memory areas other than the one being operated on.
Page 18: Restriction On Endianness
Renesas RA Family RA0 Quick Design Guide Renesas FSP configurator provides options to set up ID code protection for RA0 MCUs as shown in Figure Figure 13. ID Code Setup for RA0E1 Using Renesas FSP Configurator Note: ID code protection settings must be handled carefully to prevent mistakes that may result in blocking access to the MCU.
Page 19: Register Write Protection
Most ports on the RA0 Series of MCUs can have multiple peripheral functions. Tools, such as the Pin Configurator in FSP, are available from Renesas to assist with port selection for each RA0 device. When several peripheral functions are needed, use the following design strategies to help with port function selection.
Page 20: Setting Up And Using A Port As Gpio
Renesas FSP provides a Pin Configurator to configure the GPIO pin after reset as shown in Figure 15. Configuring P008 as Output and Low using FSP Configurator. After the GPIO is configured, it can be controlled using HAL layer APIs in FSP.
Page 21: Internal Pull-Ups
Renesas RA Family RA0 Quick Design Guide 9.2.1 Internal Pull-Ups • Most port pins can enable a pull-up resistor. The pull-up is controlled by the Pull-Up bit (PCR) bit in each Port mn Pin Function Select (PmnPFS) register. The PCR bit in each PmnPFS register controls the corresponding pin on the port.
Page 22: Setting Up And Using Irq Pins
RA0 Quick Design Guide Figure 16 shows an example of enabling SAU_SPI1 pins using FSP Pin configuration. Figure 16. Enabling SPI0 pins Using Pin Configurator in Renesas FSP 9.4 Setting Up and Using IRQ Pins • Certain port pins can be used as hardware interrupt lines (IRQ). See the Peripheral Select Settings for each Product section in the I/O Ports chapter of the Hardware User’s Manual for information on which...
Page 23: Unused Pins
Figure 17 and Figure 18 show examples of enabling and configuring IRQ pins using Renesas FSP. Figure 17. Enable P200 and P015 as IRQ0 and IRQ1 Input Using Pin Configurator in Renesas FSP Figure 18. Configure IRQ0 Using Renesas FSP Configurator 9.5 Unused Pins...
Page 24: Nonexistent Pins
0 to the corresponding bit in the MSTPCRi register. Peripherals may be stopped by writing a 1 to the proper bit in the MSTPCRi register. HAL drivers in Renesas FSP handle module start/stop function automatically. R01AN7309EU0100 Rev.1.00 Page 24 of 33 Apr.09.24...
Page 25: Interrupt Control Unit
Renesas RA Family RA0 Quick Design Guide 11. Interrupt Control Unit The Interrupt Controller Unit (ICU) controls which event signals are linked to the Nested Vector Interrupt Controller (NVIC) and Data Transfer Control (DTC) modules. The ICU also controls non-maskable interrupts.
Page 26: Low Power Consumption
Renesas RA Family RA0 Quick Design Guide Figure 21 is an example of using a Renesas FSP configurator to enable and configure an interrupt using Renesas FSP. The ICU and interrupts are configured as part of the HAL driver configuration through FSP.
Page 27 Renesas RA Family RA0 Quick Design Guide Table 10 lists the conditions to transition to low power modes, the states of the CPU and the peripheral modules, and the method for cancelling each mode. Table 10. Low Power Consumption Modes...
Page 28 The transitions to other LPMs are done by executing a WFI instruction with appropriate settings in the Standby Control register (SBYCR). Renesas FSP provides a low power mode (LPM) driver and driver configurator to set up low power mode, wake source/cancel source, and so forth.
Page 29: Buses
Application Note 13. Buses The buses in RA0 MCUs consist of a main bus and a slave interface. Figure 24 lists the main bus and the slave interface. Figure 25 shows the bus configuration. ® ® Note: Memory space must be little-endian in order to execute Arm Cortex code.
Page 30: General Layout Practices
Due to the highly multiplexed nature of the I/O pins on Renesas RA0 MCU devices, many I/O pins can be used for either analog or digital functions. This can result in situations where digital and analog functions may overlap and result in data errors.
Page 31: Signal Group Selections
The following documents were used in creating this Quick Design Guide. Visit Renesas website for the latest version of each of these documents. Reference Document Number Description R01AN6277 Renesas RA Family Design Guide for Sub-Clock Circuits R01UH1040 Renesas RA0E1 Group, User’s Manual: Hardware R01AN7309EU0100 Rev.1.00 Page 31 of 33 Apr.09.24...
Page 32 Renesas RA Family RA0 Quick Design Guide Website and Support Visit the following URLs to learn about key elements of the RA family, download components and related documentation, and get support. RA Product Information www.renesas.com/ra RA Product Support Forum www.renesas.com/ra/forum RA Flexible Software Package www.renesas.com/FSP...
Page 33: Revision History
Renesas RA Family RA0 Quick Design Guide Revision History Description Rev. Date Page Summary 1.00 Apr.09.24 — Initial release R01AN7309EU0100 Rev.1.00 Page 33 of 33 Apr.09.24...
Page 34 Unit Products The following usage notes are applicable to all Microprocessing unit and Microcontroller unit products from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
Page 35 Renesas Electronics disclaims any and all liability for any damages or losses incurred by you or any third parties arising from the use of any Renesas Electronics product that is inconsistent with any Renesas Electronics data sheet, user’s manual or other Renesas Electronics document.

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