Interrupt Mask; Table 3.24 Interrupt Mask, Address 25 (0X19) - Renesas R-IN32M4-CL2 User Manual

R-IN32M4-CL2 User's Manual Gigabit Ethernet PHY Edition
3.2.21

Interrupt Mask

These bits control the device interrupt mask. The following table shows the settings available.

Table 3.24 Interrupt Mask, Address 25 (0x19)

Bit
15 MDINT interrupt status enable
14 Speed state change mask
13 Link state change mask
12 FDX state change mask
11 Autonegotiation error mask
10 Autonegotiation complete mask
9 Reserved
8 Symbol error interrupt mask
7 Fast link failure interrupt mask
6 Reserved
5 Reserved
4 Reserved
3 False carrier interrupt mask
2 Link speed downshift detect mask
1 Master/Slave resolution error mask
0 RX_ER interrupt mask
Caution: When bit 25.15 is set, the MDINT pin is enabled. When enabled, the state of this pin reflects the state of bit 26.15.
Clearing this bit only inhibits the MDINT pin from being asserted. Also, before enabling this bit, read register 26 to
clear any previously inactive interrupts pending that will cause bit 25.15 to be set.
R18UZ0043EJ0100
Mar 4, 2016
Name Access Description
R/W Sticky bit. 1: Unmask.
R/W Sticky bit. 1: Unmask.
R/W Sticky bit. 1: Unmask.
R/W Sticky bit. 1: Unmask.
R/W Sticky bit. 1: Unmask.
R/W Sticky bit. 1: Unmask.
R/W Reserved
R/W Sticky bit. 1: Unmask.
R/W Sticky bit. 1: Unmask.
R/W Reserved
R/W Reserved
R/W Reserved
R/W Sticky bit. 1: Unmask.
R/W Sticky bit. 1: Unmask.
R/W Sticky bit. 1: Unmask.
R/W Sticky bit. 1: Unmask.
3. Registers
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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