General Purpose Registers; Reserved General Purpose Address Space; Reserved; Fast Link Failure Control - Renesas R-IN32M4-CL2 User Manual

R-IN32M4-CL2 User's Manual Gigabit Ethernet PHY Edition
3.5

General Purpose Registers

Accessing the general purpose register space is similar to accessing the extended page registers. Set register 31 to
0x0010. This sets all 32 registers to the general purpose register space.
To restore main register page access, write 0x0000 to register 31. All general purpose register bits are super-sticky
3.5.1

Reserved General Purpose Address Space

The bits in registers 0G to 18G, 20G to 24G, 26G to 28G and 30G of the general purpose register space are reserved.
3.5.2

Reserved

This register is reserved.

Table 3.38 Reserved, Address 14G (0x0E)

Bit Name
15:0 Reserved
3.5.3

Fast Link Failure Control

Register 19G in the general purpose register space controls the selection of the source PHY for the fast link failure
indication. The following table shows the settings available for the FASTLINK_FAIL pin.

Table 3.39 Fast Link Failure Control, Address 19G (0x13)

Bit
15:4 Reserved
3:0 Fast link failure port setting
3.5.4

Enhanced LED Control

The following table contains the bits to control advanced functionality of LED signals.

Table 3.40 Enhanced LED Control, Address 25G (0x19)

Bit Name
15:8 LED pulsing duty cycle control
7:1 Reserved
0 LED port swapping
R18UZ0043EJ0100
Mar 4, 2016
Access
RO
Name Access
Access
R/W
RO
R/W
Description
Reserved.
RO Reserved
R/W Select fast link failure PHY source
0000: Port0
0001: Port1
0010–1111: Output disabled
Description
Programmable control for LED pulsing duty cycle when bit
30.12 is set to 1. Valid settings are between 0 and 198. A
setting of 0 corresponds to a 0.5% duty cycle and 198
corresponds to a 99.5% duty cycle. Intermediate values
change the duty cycle in 0.5% increments
Reserved
0: LED port swapping disabled
1: LED port swapping enabled
Description
3. Registers
Default
0x2200
Default
0x000
1111
Default
0x00
0x00
0
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