Extended Phy Control 0; Error Counter 1; Error Counter 2; Table 3.16 1000Base-T Status Extension 2, Address 17 (0X11) - Renesas R-IN32M4-CL2 User Manual

R-IN32M4-CL2 User's Manual Gigabit Ethernet PHY Edition

Table 3.16 1000BASE-T Status Extension 2, Address 17 (0x11)

Bit Name
6 Reserved
5 MDI crossover error
4:0 Reserved
3.2.14

Extended PHY Control 0

The following table shows the settings available.

Table 3.17 Extended PHY Control 0, Address 18 (0x12)

Bit Name
15:8 Reserved
7 HP Auto-MDIX at forced 10/100
6 Reserved
5 Disable pair swap correction (HP
Auto-MDIX when autonegotiation
enabled)
4 Disable polarity correction
3:0 Reserved
3.2.15

Error Counter 1

The bits in register 19 provide an error counter. The following table shows the settings available.

Table 3.18 Error Counter 1, Address 19 (0x13)

Bit Name
15:8 Reserved
7:0 100/1000 receive error
counter
3.2.16

Error Counter 2

The bits in register 20 provide an error counter. The following table shows the settings available.

Table 3.19 Error Counter 2, Address 20 (0x14)

Bit Name
15:8 Reserved
7:0 100/1000 false carrier counter
R18UZ0043EJ0100
Mar 4, 2016
Access
RO Reserved
RO 1: MDI crossover error was detected
RO Reserved
Access
RO Reserved
R/W Sticky bit.
1: Disable HP Auto-MDIX at forced 10/100
speeds
RO Reserved
R/W Sticky bit.
1: Disable the automatic pair swap correction
R/W Sticky bit.
1: Disable polarity inversion correction on each
subchannel
RO Reserved
Access
RO Reserved.
RO 8-bit counter that saturates when it reaches
255. These bits are self-clearing when read.
Access
RO Reserved.
RO 8-bit counter that saturates when it reaches
255. These bits are self-clearing when read.
Description
Description
Description
Description
3. Registers
(2/2)
Default
0
0
00000
Default
0x00
1
0
0
0
1000
Default
0x00
0x00
Default
0x00
0x00
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