Interrupt Status; Table 3.25 Interrupt Status, Address 26 (0X1A) - Renesas R-IN32M4-CL2 User Manual

R-IN32M4-CL2 User's Manual Gigabit Ethernet PHY Edition
3.2.22

Interrupt Status

The status of interrupts already written to the device is available for reading from register 26 in the main registers
space. The following table shows the expected readouts.

Table 3.25 Interrupt Status, Address 26 (0x1A)

Bit Name
MDINT i
15 nterrupt status
14 Speed state change status
13 Link state change status
12 FDX state change status
11 Autonegotiation error status
10 Autonegotiation complete status
9 Reserved
8 Symbol error status
7 Fast link failure detect status
6 Reserved
5 Reserved
4 Reserved
3 False carrier interrupt status
2 Link speed downshift detect status
1 Master/Slave resolution error status
0 RX_ER interrupt status
The following information applies to the interrupt status bits:
• All set bits in this register are cleared after being read (self-clearing). If bit 26.15 is set, the cause of the interrupt can
be read by reading bits 26.14:0.
• For bits 26.14 and 26.12, bit 0.12 must be set for this interrupt to assert.
• For bit 26.2, bits 4.8:5 must be set for this interrupt to assert.
• For bit 26.0, this interrupt will not occur when RX_ER is used for carrier-extension decoding of a link partner's data
transmission.
R18UZ0043EJ0100
Mar 4, 2016
Access
RO Self-clearing bit. 1: Interrupt pending.
RO Self-clearing bit. 1: Interrupt pending.
RO Self-clearing bit. 1: Interrupt pending.
RO Self-clearing bit. 1: Interrupt pending.
RO Self-clearing bit. 1: Interrupt pending.
RO Self-clearing bit. 1: Interrupt pending.
RO Reserved
RO Self-clearing bit. 1: Interrupt pending.
RO Self-clearing bit. 1: Interrupt pending.
RO Reserved
RO Reserved
RO Reserved
RO Self-clearing bit. 1: Interrupt pending.
RO Self-clearing bit. 1: Interrupt pending.
RO Self-clearing bit. 1: Interrupt pending.
RO Self-clearing bit. 1: Interrupt pending.
Description
3. Registers
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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