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Renesas R-IN32M4-CL2 User Manual

Renesas R-IN32M4-CL2 User Manual

Gigabit ethernet phy edition
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R-IN32M4-CL2
User's Manual Gigabit Ethernet PHY Edition
R9J03G019GBG
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com)
Document number: R18UZ0043EJ0100
Issue date: Mar 4, 2016
Renesas Electronics
www.renesas.com

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Summary of Contents for Renesas R-IN32M4-CL2

  • Page 1 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
  • Page 2 Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application for which it is not intended. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for which the product is not intended by Renesas Electronics.
  • Page 3 General Precautions in the Handling of Products The following usage notes are applicable to CMOS devices from Renesas. For detailed usage notes on the products covered by this document, refer to the relevant sections of the document as well as any technical updates that have been issued for the products.
  • Page 4 1. Purpose and Target Readers This manual is intended for users who wish to understand the functions of industrial Ethernet communications ASSP (Application Specific Standard Product) “R-IN32M4-CL2” (R9J03G019GBG) and design application systems using it. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers.
  • Page 5 2. Numbers and Symbols Data significance: Higher digits on the left and lower digits on the right Active low representation: xxxZ (capital letter Z after pin or signal name) or xxx_N (capital letter _N after pin or signal name) or xxnx (pin or signal name contains small letter n) Note: Footnote for item marked with Note in the text Caution:...

  • Page 6: Table Of Contents

    Contents Product Overview ............................1 Key Features ............................... 1 1.1.1 Superior PHY and Interface Technology ....................1 1.1.2 Best in Class Power Consumption ......................1 1.1.3 Key Specifications ............................. 1 Caution in This Manual<R> ..........................1 Functional Descriptions ..........................2 Twisted Pair Media Interface ..........................
  • Page 7 3.2.4 Autonegotiation Advertisement ....................... 18 3.2.5 Link Partner Autonegotiation Capability ....................18 3.2.6 Autonegotiation Expansion ........................19 3.2.7 Transmit Autonegotiation Next Page ....................... 19 3.2.8 Autonegotiation Link Partner Next Page Receive ................... 20 3.2.9 1000BASE-T Control ..........................20 3.2.10 1000BASE-T Status ..........................21 3.2.11 1000BASE-T Status Extension 1 ......................
  • Page 8 IGURES Figure 2.1 Media Interface ............................. 2 Figure 2.2 ActiPHY State Diagram ........................5 Figure 2.3 Far-End Loopback Diagram ........................ 11 Figure 2.4 Near-End Loopback Diagram......................11 Figure 2.5 Connector Loopback Diagram ......................12 Figure 3.1 Register Space Diagram ........................13 Contents-3...
  • Page 9 ABLES Table 2.1 Supported MDI Pair Combinations ......................3 Table 2.2 LED Mode and Function Summary ......................7 Table 2.2 LED Mode and Function Summary ......................8 Table 3.1 IEEE 802.3 Registers ..........................15 Table 3.2 Main Registers ............................15 Table 3.3 Mode Control, Address 0 (0x00) ......................
  • Page 10 Table 3.33 ActiPHY Control, Address 20E1 (0x14) ..................... 33 Table 3.34 EPG Control Register 1, Address 29E1 (0x1D) .................. 34 Table 3.35 EPG Control Register 2, Address 30E1 (0x1E) ................... 35 Table 3.36 Extended Registers Page 2 Space ......................36 Table 3.37 LED Control, Address 17E2 (0x11) ....................

  • Page 11: Product Overview

    R18UZ0043EJ0100 R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition Mar 4, 2016 Product Overview The GbE-PHY is a dual-port Gigabit Ethernet PHY. The GbE-PHY is designed for space-constrained 10/100/1000BASE-T applications. It features integrated, line-side termination to conserve board space, lower EMI, and improved system performance.

  • Page 12: Functional Descriptions

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions Functional Descriptions This section describes the functional aspects of the GbE-PHY, including available operational features, and testing functionality. Twisted Pair Media Interface The twisted pair interface is compliant with IEEE 802.3-2008.

  • Page 13: Autonegotiation And Parallel Detection

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions 2.1.2 Autonegotiation and Parallel Detection The GbE-PHY supports twisted pair autonegotiation, as defined by IEEE 802.3-2008 Clause 28. The autonegotiation process evaluates the advertised capabilities of the local PHY and its link partner to determine the best possible operating mode.

  • Page 14: Manual Mdi/Mdix Setting

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions 2.1.4 Manual MDI/MDIX Setting As an alternative to HP Auto-MDIX detection, the PHY can be forced to be MDI or MDI-X using register 19E1, bits 3:2. Setting these bits to 10 forces MDI and setting 11 forces MDI-X. Leaving the bits 00 enables the HP Auto-MDIX setting to be based on register 18, bits 7 and 5.

  • Page 15: Actiphy Power Management

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions ActiPHY Power Management In addition to the IEEE-specified power-down control bit (device register bit 0.11), the GbE-PHY also includes an ActiPHY power management mode for each PHY. This mode enables support for power-sensitive applications. It utilizes a signal-detect function that monitors the media interface for the presence of a link to determine when to automatically power-down the PHY.

  • Page 16: Low Power State

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions 2.2.1 Low Power State In the low power state, all major digital blocks are powered down. However, the SMI interface (MDC, MDIO, and MDINT) functionality is provided. In this state, the PHY monitors the media interface pins for signal energy. The PHY comes out of low power state and transitions to the normal operating state when signal energy is detected on the media.

  • Page 17: Led Interface

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions LED Interface The polarity of the LED outputs is programmable and can be changed using register 17E2, bits 13:10. The default polarity is active low. It provides four LED signals per port, LED0 through LED3. The mode and function of each LED signal can be configured independently.

  • Page 18: Led Port Swapping

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions Table 2.2 LED Mode and Function Summary (2/2) Mode Function Name LED State and Description Activity 1: No activity present. Blink or pulse-stretch = Activity present. Reserved Reserved. Autonegotiation Fault 1: No autonegotiation fault present.

  • Page 19: Fast Link Failure Indication

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions Fast Link Failure Indication The GbE-PHY exceeds IEEE 802.3 standards by indicating the onset of a link failure in less than 1 ms (worst case <3 ms). (IEEE 802.3 standard establishes a delay of up to 750 ms before indicating that a 1000BASE-T link is no longer present.) A fast link failure indication is critical to support ports used in a synchronization timing link application.

  • Page 20: Testing Features

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions Testing Features The GbE-PHY includes several testing features designed to facilitate performing system-level debugging and in-system production testing. This section describes the available features. 2.5.1 Ethernet Packet Generator The Ethernet packet generator (EPG) can be used at each of the 10/100/1000BASE-T speed settings for copper media to isolate problems between the MAC and the GbE-PHY, or between a locally connected PHY and its remote link partner.

  • Page 21: Far-End Loopback

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions 2.5.2 Far-End Loopback The far-end loopback testing feature is enabled by setting register bit 23.3 to 1. When enabled, it forces incoming data from a link partner on the current media interface into the MAC interface of the PHY where it is retransmitted back to the link partner on the media interface as shown in the following illustration.

  • Page 22: Connector Loopback

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 2. Functional Descriptions 2.5.4 Connector Loopback The connector loopback testing feature allows the twisted pair interface to be looped back externally. When using this feature, the PHY must be connected to a loopback connector or a loopback cable. Connect pair A and pair B, and pair C and pair D, as shown in the following illustration.

  • Page 23: Registers

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers Registers This section provides information about how to configure the GbE-PHY using its internal memory registers and the management interface. The registers marked reserved should not be read or written to, because doing so may produce undesired effects.

  • Page 24: Register And Bit Conventions

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers Reserved Registers For main registers 16–31, extended registers 16E1–30E1, 16E2–30E2 and general purpose registers 0G–30G, any bits marked as Reserved should be processed as read-only and their states as undefined. Reserved Bits In writing to registers with reserved bits, use a read-modify-then- write technique, where the entire register is read but only the intended bits to be changed are modified.

  • Page 25: Ieee 802.3 And Main Registers

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers IEEE 802.3 and Main Registers In the GbE-PHY, the page space of the standard registers consists of the IEEE 802.3 standard registers and the GbE-PHY standard registers. The following table lists the names of the registers associated with the addresses as specified by IEEE 802.3.

  • Page 26: Mode Control

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.2.1 Mode Control The device register at memory address 0 controls several aspects of the GbE-PHY functionality. The following table shows the available bit settings in this register and what they control.

  • Page 27: Mode Status

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.2.2 Mode Status The register at address 1 in the device main registers space enables reading the currently enabled mode setting. The following table shows possible readouts of this register. Table 3.4 Mode Status, Address 1 (0x01)

  • Page 28: Autonegotiation Advertisement

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.2.4 Autonegotiation Advertisement The bits in address 4 in the main registers space control the ability to notify other devices of the status of its autonegotiation feature. The following table shows the available settings and readouts.

  • Page 29: Autonegotiation Expansion

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.2.6 Autonegotiation Expansion The bits in main register 6 work together with those in register 5 to indicate the status of the LP autonegotiation functioning. The following table shows the available settings and readouts.

  • Page 30: Autonegotiation Link Partner Next

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.2.8 Autonegotiation Link Partner Next Page Receive The bits in register 8 of the main register space work together with register 7 to determine certain aspects of the LP autonegotiation. The following table shows the possible readouts.

  • Page 31: 1000Base-T Status

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.2.10 1000BASE-T Status The bits in register 10 of the main register space can be read to obtain the status of the 1000BASE-T communications enabled in the device. The following table shows the readouts.

  • Page 32: 100Base-Tx Status Extension

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.2.12 100BASE-TX Status Extension Register 16 in the main registers page space provides additional information about the status of the 100BASE-TX operation. Table 3.15 100BASE-TX Status Extension, Address 16 (0x10) Name...

  • Page 33: Extended Phy Control 0

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers Table 3.16 1000BASE-T Status Extension 2, Address 17 (0x11) (2/2) Name Access Description Default Reserved Reserved MDI crossover error 1: MDI crossover error was detected Reserved Reserved 00000 3.2.14 Extended PHY Control 0 The following table shows the settings available.

  • Page 34: Error Counter 3

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.2.17 Error Counter 3 The bits in register 21 provide an error counter. The following table shows the settings available. Table 3.20 Error Counter 3, Address 21 (0x15) Name Access Description...

  • Page 35: Extended Phy Control 1

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.2.19 Extended PHY Control 1 The following table shows the settings available. Table 3.22 Extended PHY Control 1, Address 23 (0x17) Name Access Description Default 15:4 Reserved Reserved. 0x200 Far-end loopback mode 1: Enabled.

  • Page 36: Interrupt Mask

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.2.21 Interrupt Mask These bits control the device interrupt mask. The following table shows the settings available. Table 3.24 Interrupt Mask, Address 25 (0x19) Name Access Description Default MDINT interrupt status enable Sticky bit.

  • Page 37: Interrupt Status

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.2.22 Interrupt Status The status of interrupts already written to the device is available for reading from register 26 in the main registers space. The following table shows the expected readouts.

  • Page 38: Auxiliary Control And Status

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.2.23 Auxiliary Control and Status Register 28 provides control and status information for several device functions not controlled or monitored by other device registers. The following table shows the settings available and the expected readouts.

  • Page 39: Led Mode Select

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.2.24 LED Mode Select The device LED outputs are controlled using the bits in register 29 of the main register space. The following table shows the information needed to access the functionality of each of the outputs. For more information about LED modes, see Table 2.

  • Page 40: Extended

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers Table 3.28 LED Behavior, Address 30 (0x1E) (2/2) Name Access Description Default LED1 combine feature Sticky bit disable 0: Combine enabled (link/activity, duplex/collision) 1: Disable combination (link only, duplex only) LED0 combine feature...

  • Page 41: Extended Page 1 Registers

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers Extended Page 1 Registers To access the extended page 1 registers (16E1–30E1), enable extended register access by writing 0x0001 to register 31. Writing 0x0000 to register 31 restores the main register access.

  • Page 42: Extended Mode Control

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.3.2 Extended Mode Control Register 19E1 controls the extended modes. The following table shows the settings available. Table 3.32 Extended Mode Control, Address 19E1 (0x13) Name Access Description Default 15:5 Reserved...

  • Page 43: Table 3.33 Actiphy Control, Address 20E1 (0X14)

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers Table 3.33 ActiPHY Control, Address 20E1 (0x14) (2/2) Name Access Description Default Media mode status 00: No media selected 01: Copper media selected 10: Reserved 11: Reserved Enable 10BASE-T no preamble Sticky bit.

  • Page 44: Ethernet Packet Generator Control 1

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.3.4 Ethernet Packet Generator Control 1 The EPG control register provides access to and control of various aspects of the EPG testing feature. There are two separate EPG control registers. The following table shows the settings available in the first register.

  • Page 45: Ethernet Packet Generator Control 2

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.3.5 Ethernet Packet Generator Control 2 Register 30E1 consists of the second set of bits that provide access to and control over the various aspects of the EPG testing feature. The following table shows the settings available.

  • Page 46: Extended Page 2 Registers

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers Extended Page 2 Registers To access the extended page 2 registers (16E2–30E2), enable extended register access by writing 0x0002 to register 31. For more information, see Table 31. When extended page 2 register access is enabled, reads and writes to registers 16–30 affect the extended registers 16E2–30E2 instead of those same registers in the IEEE- specified register space.

  • Page 47: General Purpose Registers

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers General Purpose Registers Accessing the general purpose register space is similar to accessing the extended page registers. Set register 31 to 0x0010. This sets all 32 registers to the general purpose register space.

  • Page 48: Global Interrupt Status

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 3. Registers 3.5.5 Global Interrupt Status The following table contains the interrupt status from the various sources to indicate which one caused that last interrupt on the pin. Table 3.41 Global Interrupt Status, Address 29G (0x1D)

  • Page 49: Design Considerations

    R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition 4. Design Considerations Design Considerations This section provides information about design considerations for the GbE-PHY device. (1) 1000BASE-T distortion Silicon from some process corners at voltage and temperature extremes may not pass IEEE802.3 1000BASE-T distortion specification requirement of <10 mV across 60% of UI.
  • Page 50 REVISION HISTORY R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition Rev. Date Description Page Summary 0.01 Jan 15, 2016 First edition issued 1.00 Mar 4, 2016 Changed to the document format conforming the R-IN Series User's Manual. added to Section 1.2, Caution in This Manual.
  • Page 51 [Memo]...
  • Page 52 Back Cover R-IN32M4-CL2 User’s Manual Gigabit Ethernet PHY Edition...
  • Page 53 Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No. 18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: +60-3-7955-9390, Fax: +60-3-7955-9510 Renesas Electronics Korea Co., Ltd. 11F., Samik Lavied' or Bldg., 720-2 Yeoksam-Dong, Kangnam-Ku, Seoul 135-080, Korea Tel: +82-2-558-3737, Fax: +82-2-558-5141 © 2016 Renesas Electronics Corporation. All rights reserved...

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