Error Counter 3; Extended Control And Status; Table 3.20 Error Counter 3, Address 21 (0X15); Table 3.21 Extended Control And Status, Address 22 (0X16) - Renesas R-IN32M4-CL2 User Manual

R-IN32M4-CL2 User's Manual Gigabit Ethernet PHY Edition
3.2.17

Error Counter 3

The bits in register 21 provide an error counter. The following table shows the settings available.

Table 3.20 Error Counter 3, Address 21 (0x15)

Bit Name
15:8 Reserved
7:0 Copper media link disconnect
counter
3.2.18

Extended Control and Status

The bits in register 22 provide additional device control and readouts. The following table shows the settings available.

Table 3.21 Extended Control and Status, Address 22 (0x16)

Bit Name
15 Force 10BASE-T link high
14 Reserved
13 Disable 10BASE-T echo
12:10 Reserved
9 Sticky reset enable
8:1 Reserved
0 SMI broadcast write
The following information applies to the extended control and status bits:
• When bit 22.15 is set, the link integrity state machine is bypassed and the PHY is forced into a link pass status.
• When bit 22.9 is set, all sticky register bits retain their values during a software reset. Clearing this bit causes all
sticky register bits to change to their default values upon software reset. Super-sticky bits retain their values upon
software reset regardless of the setting of bit 22.9.
• When bit 22.0 is set, if a write to any PHY register (registers 0–31, including extended registers), the same write is
broadcast to all PHYs. For example, if
bit 22.0 is set to 1 and a write to PHY0 is executed (register 0 is set to 0x1040), all PHYs' register 0s are set to
0x1040. Disabling this bit restores normal PHY write operation. Reads are still possible when this bit is set, but the
value that is read corresponds only to the particular PHY being addressed.
R18UZ0043EJ0100
Mar 4, 2016
Access
RO Reserved.
RO 8-bit counter that saturates when it reaches 255. These bits are
self-clearing when read.
Access
R/W Sticky bit.
1: Bypass link integrity test
0: Enable link integrity test
RO Reserved
R/W Sticky bit.
1: Disable 10BASE-T echo
RO Reserved
R/W Super-sticky bit.
0: Enabled
RO Reserved
R/W Sticky bit.
1: Enabled
Description
Description
3. Registers
Default
0x00
0x00
Default
0
0
1
100
1
0x00
0
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