Extended Phy Control 1; Extended Phy Control 2; Table 3.22 Extended Phy Control 1, Address 23 (0X17); Table 3.23 Extended Phy Control 2, Address 24 (0X18) - Renesas R-IN32M4-CL2 User Manual

R-IN32M4-CL2 User's Manual Gigabit Ethernet PHY Edition
3.2.19

Extended PHY Control 1

The following table shows the settings available.

Table 3.22 Extended PHY Control 1, Address 23 (0x17)

Bit Name
15:4 Reserved
3 Far-end loopback mode
2:0 Reserved
3.2.20

Extended PHY Control 2

The second set of extended controls is located in register 24 in the main register space for the device. The following
table shows the settings and readouts available.

Table 3.23 Extended PHY Control 2, Address 24 (0x18)

Bit Name
15:6 Reserved
5:4 Jumbo packet mode
3:1 Reserved
1000BASE-T connector loopback
0
Caution: When bits 5:4 are set to jumbo packet mode, the default maximum packet values are based on 100 ppm driven
reference clock to the device. Controlling the ppm offset between the MAC and the PHY as specified in the bit
description results in a higher jumbo packet length.
R18UZ0043EJ0100
Mar 4, 2016
Access
RO Reserved.
R/W 1: Enabled.
RO Reserved.
Access
RO Reserved
R/W Sticky bit.
00: Normal IEEE 1.5 kB packet length
01: 9 kB jumbo packet length (12 kB with
60 ppm or better reference clock)
10: 12 kB jumbo packet length (16 kB with
70 ppm or better reference clock)
11: Reserved
RO Reserved
R/W 1: Enabled
Description
Description
3. Registers
Default
0x200
0
000
Default
0x000
00
000
0
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