Extended Page 1 Registers; Cu Media Crc Good Counter; Table 3.30 Extended Registers Page 1 Space; Table 3.31 Cu Media Crc Good Counter, Address 18E1 (0X12) - Renesas R-IN32M4-CL2 User Manual

R-IN32M4-CL2 User's Manual Gigabit Ethernet PHY Edition
3.3

Extended Page 1 Registers

To access the extended page 1 registers (16E1–30E1), enable extended register access by writing 0x0001 to register 31.
Writing 0x0000 to register 31 restores the main register access.
When extended page 1 register access is enabled, reads and writes to registers 16–30 affect the extended registers
16E1–30E1 instead of those same registers in the IEEE- specified register space. Registers 0–15 are not affected by the
state of the extended page register access.

Table 3.30 Extended Registers Page 1 Space

Address
16E1–17E1
18E1
19E1
20E1
21E1–28E1
29E1
30E1
3.3.1

Cu Media CRC Good Counter

Register 18E1 makes it possible to read the contents of the CRC good counter for packets that are received on the Cu
media interface; the number of CRC routines that have executed successfully. The following table shows the expected
readouts.

Table 3.31 Cu Media CRC Good Counter, Address 18E1 (0x12)

Bit Name
15 Packet since last read
14 Reserved
13:0 Cu Media CRC good counter
contents
R18UZ0043EJ0100
Mar 4, 2016
Reserved
Cu Media CRC good counter
Extended mode control
ActiPHY control
Reserved
EPG Control Register 1
EPG Control Register 2
Access
RO Self-clearing bit.
1: Packet received since last read.
RO Reserved.
RO Self-clearing bit. Counter containing the number of packets with
valid CRCs modulo 10,000; this counter does not saturate and
will roll over to zero on the next good packet received after
9,999.
Name
Description
3. Registers
Default
0
0
0x0000
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