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80C196KB USER'S GUIDE
MODES OF OPERATION
Mode 0 is a synchronous mode which is commonly
used for shift register based I O expansion Sets of 8
bits are shifted in or out of the 80C196KB with a data
signal and a clock signal
Mode 1 is the standard asynchronous communications
mode the data frame used in this mode consists of 10
bits a start bit (0) 8 data bits (LSB first) and a stop bit
(1) Parity can be enabled to send an even parity bit
instead of the 8th data bit and to check parity on recep-
tion
Modes 2 and 3 are 9-bit modes commonly used for
multi-processor communications The data frame used
in these modes consist of a start bit (0) 9 data bits (LSB
first) and a stop bit (1) When transmitting the 9th
data bit can be set to a one to indicate an address or
other global transmission Devices in Mode 2 will be
interrupted only if this bit is set Devices in Mode 3 will
be interrupted upon any reception This provides an
easy way to have selective reception on a data link
Mode 3 can also be used to send and receive 8 bits of
data plus even parity
BAUD RATES
Baud rates are generated in an independent 15-bit
counter based on either the T2CLK pin or XTAL1 pin
Common baud rates can be easily generated with stan-
dard crystal frequencies A maximum baud rate of 750
Kbaud is available in the asynchronous modes with
12MHz on XTAL1 The synchronous mode has a max-
imum rate of 3 0 Mbaud with a 12 MHz clock
4 6 A D Converter
The 80C196KB's Analog interface consists of a sample-
and-hold an 8-channel multiplexer and a 10-bit suc-
cessive approximation analog-to-digital converter
Analog signals can be sampled by any of the 8 analog
input pins (ACH0 through ACH7) which are shared
with Port 0 An A D conversion is performed on one
26
input at a time using successive approximation with a
result equal to the ratio of the input voltage divided by
the analog supply voltage If the ratio is 1 00 then the
result will be all ones A conversion can be started by
writing to the A D Command register or by an HSO
Command Details on the A D converter are in Section
11
4 7 I O Ports
There are five 8-bit I O ports on the 80C196KB Some
of these ports are input only some are output only
some are bidirectional and some have multiple func-
tions In addition to these ports the HSI O pins can be
used as standard I O pins if their timer related features
are not needed
Port 0 is an input port which is also the analog input
for the A D converter Port 1 is a quasi-bidirectional
port and the 3MSBs of Port 1 are multiplexed with the
HOLD HLDA functions Port 2 contains three types
of port lines quasi-bidirectional input and output Its
input and output lines are shared with other functions
such as serial port receive and transmit and Timer2
clock and reset Ports 3 and 4 are open-drain bidirec-
tional ports which share their pins with the address
data bus
Quasi-bidirectional pins can be used as input and out-
put pins without the need for a data direction register
They output a strong low value and a weak high value
The weak high value can be externally pulled low pro-
viding an input function A detailed explanation of
these ports can be found in Section 12
4 8 Watchdog Timer
The Watchdog Timer (WDT) provides a means to re-
cover gracefully from a software upset When the
watchdog is enabled it will initiate a hardware reset
unless the software clears it every 64K state times
Hardware resets on the 80C196KB cause the RESET
input pin to be pulled low providing a reset signal to
other components on the board The WDT is indepen-
dent of the other timers on the 80C196KB
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