Page 1 Spartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 2 Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.
Page 3: Table Of Contents
... . . 22 Spartan-3A/3AN FPGA Features and Embedded Processing Functions ..22 Other Spartan-3 Generation Development Boards ......23 Spartan-3A and Spartan-3AN FPGAs .
Page 4 ............50 Display On/Off www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 5 ..........77 Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com...
Page 6 ............113 www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide...
Page 7 ............139 Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com...
Page 8 FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 9 There are multiple versions of the Spartan-3A/3AN FPGA Starter Kit. This document describes the three kits that include the “Revision D” Spartan-3A/3AN FPGA Starter Kit Board, which is an updated version of the “Revision C” Spartan-3A FPGA Starter Kit Board. The following table describes the different kits.
Page 10: Preface: About This Guide
Preface: About This Guide Board Revision Code REV C UG334_01_052707 Acknowledgments Xilinx wishes to thank the following companies for their support of the Spartan-3A/3AN Starter Kit board: • STMicroelectronics for the 32 Mbit parallel NOR Flash and 16 Mbit SPI serial Flash memories •...
Page 11: Additional Resources
To find additional documentation, see the Xilinx website at: http://www.xilinx.com/support/documentation/index.htm To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: http://www.xilinx.com/support. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com...
Page 12 Preface: About This Guide www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 13: Chapter 1: Introduction And Overview
Spartan-3A or Spartan-3AN FPGA application. Getting Started The Spartan-3A/3AN Starter Kit board is ready for use, right out of the box. The design stored in external Flash exercises the various I/O devices, such as the VGA display and serial ports.
Page 14 Figure 1-2: Default Jumper Settings for Starter Kit Board For more information on the demonstration design, visit the Design Examples web page: • Spartan-3A/3AN FPGA Starter Kit Demo Design Overview www.xilinx.com/products/boards/s3astarter/reference_designs.htm#demo • Restoring the “Out of the Box” Flash Programming www.xilinx.com/products/boards/s3astarter/reference_designs.htm#out...
Page 15: Operating The Default Demonstration Design
UG330_c1_03_032207 Figure 1-3: Rotating/Zooming Graphics, Menu System Displayed on VGA Screen Rotary Knob/Push-Button Menu System The Spartan-3A/3AN Starter Kit board demonstration design uses the rotary knob and surrounding push-button switches, shown in Figure 2-5, page 27, to implement a menu system.
Page 16: Select Multiboot Configuration Image
Figure 1-4: Rotary Knob/Push-Button Menu System Select MultiBoot Configuration Image Spartan-3A/3AN FPGAs support a selectable MultiBoot configuration interface. If the FPGA configures in one of its Master configuration modes, then the FPGA always loads the configuration image stored at address 0 in Flash at power-up, or whenever the PROG_B button is pressed.
Page 17: Scroll Or Rotate Graphic
In this mode, rotate the knob to control the speaker output volume. Press any of the four push-button switches to restart the AutoPilot function. Press the rotary knob to change to the “Select MultiBoot Configuration Image” mode. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 18: Lcd Screen Control Option
Suspend mode reduces FPGA power consumption while preserving the present state of the FPGA application and the FPGA’s configuration data. Set the SUSPEND switch to RUN or SUSPEND as described in “SUSPEND Switch,” page www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 19: Rs-232 Serial Port Control Option
Press a number key on the PC to load the associated MultiBoot bitstream listed in Table 1-2. Key Components and Features The key features of the Spartan-3A FPGA Starter Kit board or the Spartan-3AN FPGA Starter Kit board are: • Spartan-3A FPGA Starter Kit Board: Xilinx 700K-gate XC3S700A...
Page 20 Stereo audio jack using digital I/O pins • ChipScope™ SoftTouch debugging port • Rotary-encoder with push-button shaft • Eight discrete LEDs • Four slide switches • Four push-button switches www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 21: Design Trade-Offs
Xilinx Platform USB cable. Voltages for all Applications The Spartan-3A/3AN FPGA typically operates with two supply rails, 1.2V and 3.3V. The Spartan-3A/3AN Starter Kit board showcases a quadruple-output regulator developed by National Semiconductor specifically to power Spartan-3 generation FPGAs. This regulator is sufficient for most standalone FPGA applications.
Page 22: Choose A Spartan-3 Generation Starter Kit Board For Your Needs
This design uses a PicoBlaze™ processor to read the unique “Device DNA” identifier embedded in each Spartan-3A/3AN FPGA and then display it on the LCD screen. Choose a Spartan-3 Generation Starter Kit Board for your Needs The Spartan-3A and Spartan-3AN Starter Kit boards are best for prototyping Spartan-3A/3AN FPGA applications.
Page 23: Other Spartan-3 Generation Development Boards
Spartan-3AN FPGAs require V to be 3.3V while Spartan-3A FPGAs allow V CCAUX CCAUX to be either 2.5V or 3.3V. The Spartan-3A/3AN Starter Kit Board uses a default V CCAUX 3.3V. Spartan-3A and Spartan-3AN FPGAs have different documentation and availability. Verify the latest version of the appropriate documentation on xilinx.com.
Page 24: Related Resources
Related Resources Refer to the following links for additional information: • Spartan-3A/3AN Starter Kit www.xilinx.com/s3astarter ♦ Spartan-3A/3AN Rev D Starter Kit user guide (this document) ♦ Spartan-3A Rev C Starter Kit user guide www.xilinx.com/support/documentation/boards_and_kits/ug330.pdf ♦ Example User Constraints File (UCF) www.xilinx.com/products/boards/s3astarter/files/s3astarter.ucf...
Page 25: Chapter 2: Switches, Buttons, And Rotary Knob
I/O standard used. The PULLUP resistor is not required, but it defines the input value when the switch is in the middle of a transition. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 26: Suspend Switch
Figure 2-4: UCF Constraints to Enable Suspend Mode For more information on Suspend mode, see the following application note: • XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs www.xilinx.com/support/documentation/application_notes/xapp480.pdf www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 27: Push-Button Switches
Push-Button Switches Push-Button Switches Locations and Labels The Spartan-3A/3AN Starter Kit board has four momentary-contact push-button switches, shown in Figure 2-5. The push buttons are located in the lower right corner of the board and are labeled BTN_NORTH, BTN_EAST, BTN_SOUTH, and BTN_WEST. The...
Page 28: Prog_B Push-Button Switch
2-8. Use an internal pull-down resistor within the FPGA pin to generate a logic Low. Figure 2-11 shows how to specify a pull-down resistor within the UCF. There is no active debouncing circuitry on the push button. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 29: Rotary Shaft Encoder
As shown in Figure 2-10, the chatter can falsely indicate extra rotation events or even indicate rotations in the opposite direction! Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 30: Ucf Location Constraints
PULLDOWN Figure 2-11: UCF Constraints for Rotary Push-Button Switch Discrete LEDs Locations and Labels The Spartan-3A/3AN Starter Kit board has eight individual surface-mount LEDs located immediately above the slide switches as shown in Figure 2-12. The LEDs are labeled LED7 through LED0.
Page 31: Operation
= SLOW | DRIVE Figure 2-13: UCF Constraints for Eight Discrete LEDs Optional Discrete LEDs The Spartan-3A/3AN Starter Kit board provides two optional LEDs, shown in Figure 2-14. Depending on which features are used by an application, these LED connections may be also used as user-I/O pins.
Page 32: Awake Led
40, must be in either the “Disabled” or “Enabled during Configuration” setting. The “Always Enabled” setting for Jumper J46 allows the FPGA to read additional data from the Platform Flash PROM after configuration, as described in Xilinx application note XAPP694. Caution! The FPGA’s INIT_B pin also connects to the Platform Flash PROM’s OE/RESET pin.
Page 33: Chapter 3: Clock Sources
A 133 MHz clock oscillator is installed in the CLK_AUX socket. Optionally substitute a separate eight-pin DIP-style clock oscillator in the provided socket. CLK_50MHZ (E12) CLK_AUX (V12) CLK_SMA (U12) UG334_c3_01_052407 Figure 3-1: Clock Sources on Starter Kit Board Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 34: Clock Connections
Location Figure 3-2 provides the UCF constraints for the three clock input sources, including the I/O pin assignment and the I/O standard used. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 35: Clock Period Constraints
40%; Figure 3-3: UCF Clock PERIOD Constraint Related Resources Refer to the following links for additional information: • Epson SG-8002JF Series Oscillator Data Sheet (50 MHz Oscillator) http://www.eea.epson.com/portal/pls/portal/docs/1/793426.PDF Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 36 Chapter 3: Clock Sources www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 37: Chapter 4: Fpga Configuration Options
This option is not available in the Spartan-3A Starter Kit. • Download FPGA designs directly to the Spartan-3A/3AN FPGA via JTAG, using the on-board USB interface. The on-board USB-JTAG logic also provides in-system programming for the on-board Platform Flash PROM. SPI serial Flash and StrataFlash programming are performed separately.
Page 38 The DONE pin LED lights when the FPGA successfully finishes configuration. Pressing the PROG button forces the FPGA to restart its configuration process. The Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial mode.
Page 39: Configuration Mode Jumpers
0 and incrementing through address “Parallel NOR Flash space. PROM”) Disable the Platform Flash PROM via J46 jumper per Table 4-2. JTAG 1:0:1 Downloaded from host via USB-JTAG port Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 40: Xilinx Platform Flash Configuration Prom(S)
Chapter 4: FPGA Configuration Options Xilinx Platform Flash Configuration PROM(s) The Spartan-3A/3AN Starter Kit board includes a Xilinx Platform Flash configuration interface. A single 4 Mbit XCF04S Platform Flash PROM appears in the JTAG chain with the FPGA. Caution! The J46 jumper, shown in...
Page 41: Done Pin Led
Figure 4-2: Standard USB Type A/Type B Cable The wider and narrower Type A connector fits the USB connector at the back of the computer. After installing the Xilinx software, connect the square Type B connector to the Spartan- 3A/3AN Starter Kit board, as shown in Figure 4-3.
Page 42: Platform Flash Programming Example
When the USB cable driver is successfully installed and the board is correctly connected to the PC, a green LED lights up, indicating that the programming cable is ready. The USB connection also has a red LED, which only lights if the Xilinx software is programming firmware updates to the USB interface.
Page 43: Chapter 5: Character Lcd Screen
Chapter 5 Character LCD Screen Overview The Spartan-3A/3AN Starter Kit board prominently features a 2-line by 16-character liquid crystal display (LCD). The FPGA controls the LCD via the eight-bit data interface shown in Figure 5-1. The Spartan-3A/3AN Starter Kit board also supports the four-bit data interface to remain compatible with other Xilinx development boards.
Page 44: Character Lcd Interface Signals
UCF Location Constraints Figure 5-2 provides the UCF constraints for the Character LCD, including the I/O pin assignment and the I/O standard used. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 45: Lcd Controller
Locations 0x10 through 0x27 and 0x50 through 0x67 can be used to store other non-display data. Alternatively, these locations can also store characters that can only be displayed using controller’s display shifting functions. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 46: Cg Rom
DB[3:0] = 0011 binary. As shown in Figure 5-4, the character ‘S’ appears on the screen. English/Roman characters are stored in CG ROM at their equivalent ASCII code addresses. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 47: Cg Ram
CG RAM. Write CG RAM data using the Write Data to CG RAM or DD RAM command, and read CG RAM using the Read Data from CG RAM or DD RAM command. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 48: Command Set
Table 5-2: LCD Character Display Command Set (4-bit mode) Upper Nibble Lower Nibble Function Clear Display Return Cursor Home Entry Mode Set Display On/Off Cursor and Display Shift www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 49: Disabled
This bit either auto-increments or auto-decrements the DD RAM and CG RAM address counter by one location after each Write Data to CG RAM or DD RAM command or Read Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 50: Display On/Off
When the displayed data is shifted repeatedly, both lines move horizontally. The second display line does not shift into the first display line. Execution Time: 40 µs www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 51: Function Set
Writes data into DD RAM if the command follows a previous Set DD RAM Address command, or writes data into CG RAM if the command follows a previous Set CG RAM Address command. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 52: Read Data From Cg Ram Or Dd Ram
However, a display shift is not executed during read operations. Execution Time: 40 µs Operation The board has an eight-bit data interface to the character LCD. Other Xilinx boards use a four-bit interface. As shown in Figure 5-1, the Spartan-3A/3AN Starter Kit board supports both an eight-bit and a four-bit interface for compatibility reasons.
Page 53: Transferring Eight-Bit Data Over The Four-Bit Interface
The initialization sequence is simple and ideally suited to the highly-efficient eight-bit PicoBlaze embedded controller. After initialization, the PicoBlaze controller is available for more complex control or computation beyond simply driving the display. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 54: Power-On Initialization
Continuing to write characters, however, eventually falls off the end of the first display line. The additional characters do not automatically appear on the second line because the DD RAM map is not consecutive from the first line to the second. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 55: Disabling The Unused Lcd
• Sitronix ST7066U Character LCD Controller www.samsung.com/global/business/semiconductor/productInfo.do?fmly_id=204& partnum=S6A0069 • Samsung S6A0069X Character LCD Controller www.samsung.com/Products/Semiconductor/DisplayDriverIC/MobileDDI/ BWSTN/S6A0069X/S6A0069X.htm • Design Example: Device DNA Reader and LCD Display Controller www.xilinx.com/products/boards/s3astarter/reference_designs.htm#dna_reader Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 56 Chapter 5: Character LCD Screen www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 57: Chapter 6: Vga Display Port
The FPGA directly drives the five VGA signals via resistors. Each red, green, and blue signal has four outputs from the FPGA that feed a resistor-divider tree. This approach Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 58: Signal Timing For A 60 Hz, 640X480 Vga Display
CRT displays, LCDs have evolved to use the same signal timings as CRT displays. Consequently, the following discussion pertains to both CRTs and LCDs. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 59 Modern VGA displays support multiple display resolutions, and the VGA controller dictates the resolution by producing timing signals to control the raster patterns. The controller produces TTL-level synchronizing pulses that set the frequency at which current Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 60: Vga Signal Timing
Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location. The Spartan-3A/3AN Starter Kit board uses 12 bits per pixel, producing one of the 4,096 possible colors. The controller indexes into the video data buffer as the beams move across the display.
Page 61: Ucf Location Constraints
= FAST ; Figure 6-4: UCF Constraints for VGA Display Port Related Resources Refer to the following links for additional information: • VESA www.vesa.org • VGA timing information www.epanorama.net/documents/pc/vga_timing.html Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 62 Chapter 6: VGA Display Port www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 63: Chapter 7: Rs-232 Serial Ports
9-pin serial cable TALK/DATA RS CS TR RD TD CD TALK Female DB9 Male DB9 RS-232 Voltage Translator (IC3) (E16) (F15) (F16) (E15) FPGA UG334_c7_01_052407 Figure 7-1: RS-232 Serial Ports Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 64: Ucf Location Constraints
= LVCMOS33 ; NET "RS232_DCE_TXD" = "F15" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW Figure 7-3: UCF Location Constraints for DCE RS-232 Serial Port www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 65: Chapter 8: Ps/2 Mouse/Keyboard Port
Primary data connection PS2_DATA1 Secondary data connection when using PS/2 splitter cable PS2_DATA2 No Connection Primary clock connection PS2_CLK1 Secondary data connection with using PS/2 splitter cable PS2_CLK2 Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 66: Keyboard
When a key is released, the keyboard sends an “F0” key-up code, followed by the scan code of the released key. The keyboard sends the same scan code, regardless if a key has www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 67 The clock line can be used as a clear to send signal. If the host pulls the clock line Low, the keyboard must not send any data until the clock is released. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com...
Page 68: Mouse
‘1’ indicates a negative value. +Y values (YS=0) -X values +X values (XS=1) (XS=0) -Y values (YS=1) UG230_c8_05_021806 Figure 8-5: The Mouse Uses a Relative Coordinate System to Track Movement www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 69: Voltage Supply
A ‘1’ indicates that the associated mouse button is being pressed. Voltage Supply The PS/2 port on the Spartan-3A/3AN Starter Kit board is powered by 5V. Although the Spartan-3A/3AN FPGA is not a 5V-tolerant device, it can communicate with a 5V device using 270Ω...
Page 70: Ucf Location Constraints
Figure 8-7: UCF Location Constraints for PS/2 Port Related Resources Refer to the following links for additional information: • PS/2 Mouse/Keyboard Protocol www.computer-engineering.org/ps2protocol • PS/2 Keyboard Interface www.computer-engineering.org/ps2keyboard • PS/2 Mouse Interface www.computer-engineering.org/ps2mouse www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 71: Chapter 9: Analog Capture Circuit
J22 header. The output of the pre- amplifier connects to a Linear Technology LTC1407A-1 ADC. Both the pre-amplifier and the ADC are serially programmed or controlled by the FPGA. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 72: Digital Outputs From Analog Inputs
VINA or VINB. The maximum range of the ADC is ±1.25V, centered around the reference voltage, 1.65V. Hence, 1.25V appears in the denominator to scale the analog input accordingly. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 73: Programmable Pre-Amplifier
The gain of each amplifier is programmable from -1 to -100, as shown in Table 9-2. Table 9-2: Programmable Gain Settings for Pre-Amplifier Input Voltage Range Gain Minimum Maximum 1.025 2.275 Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 74: Spi Control Interface
All timing is minimum in nanoseconds unless otherwise noted. UG230_c10_04_022306 Figure 9-4: SPI Timing When Communicating with Amplifier The amplifier interface is relatively slow, supporting only about a 10 MHz clock frequency. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 75: Ucf Location Constraints
The maximum sample rate is approximately 1.5 MHz. The ADC presents the digital representation of the sampled analog values as a 14-bit, two’s complement binary value. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 76: Ucf Location Constraints
IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ; "AD_DOUT" = "D16" IOSTANDARD = LVCMOS33 ; Figure 9-8: UCF Location Constraints for the ADC Interface www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 77: Connecting Analog Inputs
Refer to the following links for additional information: • Xilinx PicoBlaze Soft Processor http://www.xilinx.com/picoblaze • LTC6912 Dual Programmable Gain Amplifiers with Serial Digital Interface http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1154,C1009,C1121,P7596,D5359 • LTC1407A-1 Serial 14-bit Simultaneous Sampling ADCs with Shutdown http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1001,C1158,P2420,D1295 Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 78 Chapter 9: Analog Capture Circuit www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 79: Chapter 10: Digital-To-Analog Converter (Dac)
FPGA in this example—drives the bus clock signal (SPI_SCK) and transmits serial data (SPI_MOSI) to the selected bus slave—the DAC in this example. At the same time, the bus slave provides serial data (SPI_MISO) back to the bus master. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 80: Interface Signals
SPI_SCK clock signal. The bus is fully static and supports clock rates up to the maximum of 50 MHz. However, check all timing parameters using the LTC2624 data sheet if operating at or close to the maximum speed. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 81: Communication Protocol
0 0 0 1 DAC B 0 0 1 0 DAC C 0 0 1 1 DAC D 1 1 1 1 UG334_c10_04_052407 Figure 10-4: SPI Communications Protocol to LTC2624 DAC Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 82: Specifying The Dac Output Voltage
Related Resources Refer to the following links for additional information: • LTC2624 Quad DAC Data Sheet http://www.linear.com/pc/downloadDocument.do?navId=H0,C1,C1155,C1005,C1156,P2048,D2170 • Xilinx PicoBlaze Soft Processor http://www.xilinx.com/picoblaze • Digilent, Inc. Peripheral Modules http://www.digilentinc.com/Products/Catalog.cfm?Nav1=Products&Nav2=Peripheral&Cat=Peripheral www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 83: Chapter 11: Parallel Nor Flash Prom
Stores MicroBlaze processor code in the Flash memory and shadows the code into the DDR2 SDRAM memory before executing the code. • Stores non-volatile user data from the FPGA application. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 84: Flash Connections
Although the XC3S700A/AN FPGA only requires just slightly over 2.6 Mbits per uncompressed configuration image, the FPGA-to-Flash interface on the board supports up to a 256 Mbit Flash. The Spartan-3A/3AN Starter Kit board ships with a 32 Mbit device. Address lines SF_A<25:22> are not used.
Page 85 Bit 0 of a data byte and a 16-bit halfword. (SPI_MISO) Connects to FPGA pin D0/DIN to support the BPI configuration. Shared with other SPI peripherals and Platform Flash PROM. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 86: Shared Spi Flash And Platform Flash Data Line
SPI serial Flash PROMs and the serial output from the Platform Flash PROM as shown in Table 11-2, page 87. To avoid contention, the FPGA application must ensure that only one data source is active at any time. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 87: Ucf Location Constraints
# They are available as user I/Os but do not connect to anything on the board CONFIG PROHIBIT = B22; CONFIG PROHIBIT = B21; CONFIG PROHIBIT = G18; CONFIG PROHIBIT = G17; Figure 11-2: UCF Location Constraints for Flash Address Signals Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 88: Data
Table 11-3. The Spartan-3A/3AN FPGA families do not support the BPI Down mode that is available in the Spartan-3E FPGA family. Also be sure to disable the Platform Flash PROM by removing jumper J46, as shown in Table 11-3.
Page 89: Creating And Programming Configuration Images For Parallel Flash
Refer to the following links for additional information: • STMicroelectronics M29DW323DT 32 Mbit Parallel NOR Flash PROM www.numonyx.com/Documents/Datasheets/M29DW323D.pdf • Design Example: Programmer for the STMicroelectronics M29DW323DT Parallel NOR Flash www.xilinx.com/products/boards/s3astarter/reference_designs.htm#parallel_flash _programmer Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 90 Chapter 11: Parallel NOR Flash PROM www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 91: Chapter 12: Spi Serial Flash
The SPI serial Flash is useful in a variety of applications. The SPI Flash provides a possible means to configure the FPGA—a new feature in Spartan-3E and Spartan-3A/3AN FPGAs. The SPI Flash is also available to the FPGA after configuration for a variety of purposes, such as: •...
Page 92 PROM. Has external 4.7kΩ pull-up resistor. ST_SPI_WP Write-protect input to ST M25P16 PROM. Must be High to program the FPGA PROM PROM. Has external 4.7kΩ pull-up resistor. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 93: Spi Flash Prom Select Jumpers (J1)
Slave Select Signal Slave Select Signal Atmel SPI_SS_B AT45DB161D (Y4) STMicro SPI_SS_B M25P16 (Y4) Atmel SPI_SS_B ALT_SS_B AT45DB161D (Y4) (Y5) STMicro ALT_SS_B SPI_SS_B M25P16 (Y5) (Y4) None None None Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 94: Shared Spi Flash And Platform Flash Data Line
Jumper J26 Settings Enable (J46) Master SPI 0:0:1 DONE PROM • Select one of the SPI serial Flash PROMs as the SPI configuration source, as shown in Table 12-2. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 95: Ucf Location Constraints
Refer to the “Master SPI Mode” chapter in the Spartan-3 Generation Configuration User Guide for information on how to create and format FPGA configuration images for SPI serial Flash and how to program SPI Flash using the Xilinx iMPACT software. •...
Page 96: Direct Programming Method
STMicro PROM Atmel PROM ROM-CS0 CSO-SEL ROM-CS0 CSO-SEL CSO-B ROM-CS1 CSO-B ROM-CS1 JTAG Header SPI Header PROG_B PROG_B UG330_c15_05_032907 Figure 12-4: Jumper Settings for Direct SPI Flash Programming www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 97: Using A Separate Jtag Parallel Programming Cable (Optional)
Connect the cable directly to the J23 header block, as illustrated in Figure 12-5. These cables are not provided with the Spartan-3A/3AN Starter Kit board but can be purchased separately. a) JTAG3 Parallel Connector b) Parallel Cable III or Parallel Cable IV...
Page 98: Direct Spi Flash Programming Using Impact
Click Direct SPI Configuration from within iMPACT, as shown in Figure 12-6. UG332_c4_03_101006 Figure 12-6: iMPACT Supports Direct Programming for SPI Serial Flash Memories Right-click in the area indicated. Select Add SPI Device. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 99 Click Open. Select the Part Name for a supported SPI serial Flash, as shown in Figure 12-8. UG332_c4_05_101006 Figure 12-8: Select a Supported SPI Flash Memory Device Click OK. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 100 UG332_c4_07_101006 Figure 12-10: SPI PROM Programming Options 11. Check Verify. Unchecking Verify reduces programming time but the iMPACT software can only guarantee correct programming for a verified PROM. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 101: Indirect Programming Method
18. Reapply power. Indirect Programming Method Indirect programming support is available starting with Xilinx ISE 9.1i, Service Pack 2 and later releases. In Indirect mode, the iMPACT software programs the memory attached to the FPGA through the FPGA’s JTAG port.
Page 102: Indirect Spi Flash Programming Using Impact
Indirect programming method, follow the steps outlined below. Invoke iMPACT and select Configure devices using Boundary Scan (JTAG), as shown in Figure 12-11. UG332_c4_22_032807 Figure 12-11: Indirect Programming Method Uses JTAG Select Finish. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 103 TCK. The SPI Flash image is not affected. This warning is safely ignored. UG332_c4_24_032807 Figure 12-13: iMPACT Uses the JTAG Clock Input TCK for Startup Clock when Programming via JTAG Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 104 Click Open. Select the part number for the attached SPI Flash PROM, as shown in Figure 12-15. UG332_c4_27_032907 Figure 12-15: Select SPI Flash PROM Type 10. Click OK. www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 105 Figure 12-17, the iMPACT software then displays the JTAG chain for the XC3S700A Spartan-3A FPGA followed by the XCF04S Platform Flash PROM. A similar display will be seen for the XC3S700AN Spartan-3AN FPGA. Click to highlight the FLASH memory attached to the XC3S700A FPGA. This action enables the command options shown in Step 13.
Page 106: Related Resources
15. Check Verify. Unchecking Verify reduces programming time but the iMPACT software can only guarantee correct programming for a verified PROM. 16. Check Erase Before Programming. Unchecking the Erase option reduces programming time. However, Xilinx recommends erasing the PROM when downloading a new FPGA bitstream. 17. Click OK.
Page 107: Chapter 13: Ddr2 Sdram
LDQS# SD_LDQS_P (K3) LDQS SD_CS (M5) SD_CKE (N3) SD_CK_N (M2) SD_CK_P (M1) SD_ODT (P1) (H4) (H3) SD_LOOP UG334_c13_01_052407 Figure 13-1: FPGA Interface to Micron 512 Mbit DDR2 SDRAM Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 108: Ddr2 Sdram Connections
Unused on 512 Mbit DDR2 SDRAM device but provided for potential future upgrades SD_A14 SD_A13 SD_A12 Address inputs SD_A11 SD_A10 SD_A9 SD_A8 SD_A7 SD_A6 SD_A5 SD_A4 SD_A3 SD_A2 SD_A1 SD_A0 www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 109 Active-High clock enable input SD_CS Active-Low chip select input SD_UDM Data Mask. Upper and Lower data masks. SD_LDM SD_UDQS_N Upper differential data strobe SD_UDQS_P SD_LDQS_N Lower differential data strobe SD_LDQS_P Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 110: Ucf Location Constraints
= SSTL18_II ; "SD_A<1>" = "T4" | IOSTANDARD = SSTL18_II ; "SD_A<0>" = "R2" | IOSTANDARD = SSTL18_II ; Figure 13-2: UCF Location Constraints for DDR2 SDRAM Address Inputs www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 111: Data
= SSTL18_II ; "SD_LOOP_IN" = "H4" | IOSTANDARD = SSTL18_II ; "SD_LOOP_OUT" = "H3" | IOSTANDARD = SSTL18_II ; Figure 13-4: UCF Location Constraints for DDR2 SDRAM Control Pins Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 112: Reserve Fpga Vref Pins
FPGA. Put another way, the loopback trace must be one round trip time to and from the memory. Also, the loopback signal should be in the center of the data interface pins for best results, not near the edge or in another FPGA I/O bank. The Spartan-3A/3AN Starter Kit board was designed accordingly.
Page 113: Related Resources
Xilinx Embedded Development Kit (EDK) www.xilinx.com/ise/embedded_design_prod/platform_studio.htm • MT47H32M16 (32M x 16) DDR2 SDRAM Data Sheet download.micron.com/pdf/datasheets/dram/ddr2/512MbDDR2.pdf • Multi-Channel OPB DDR2 Controller Xilinx IP Core www.xilinx.com/support/documentation/ip_documentation/mch_opb_ddr2.pdf • Memory Interface Generator (MIG), Version 1.7 or later www.xilinx.com/memory Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com...
Page 114 Chapter 13: DDR2 SDRAM www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 115 25 MHz crystal oscillator. RJ-45 Ethernet Connector (J32) (integrated magnetics) SMSC LAN8700 10/100 Ethernet PHY 25 MHz Crystal UG334_c14_01_052407 Figure 14-1: 10/100 Ethernet PHY with RJ-45 Connector Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 116: Chapter 14: 10/100 Ethernet Physical Layer Interface
E_TXD<0> E_TX_EN Transmit Enable E_TX_CLK Transmit Clock. 25 MHz in 100Base-TX mode and 2.5 MHz in 10Base-T mode. E_RXD<4> Receive Data from the PHY E_RXD<3> E_RXD<2> E_RXD<1> E_RXD<0> www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 117: Microblaze Ethernet Ip Cores
65 MHz or higher for 100 Mbps Ethernet operations and 6.5 MHz or faster for 10 Mbps Ethernet operations. The hardware evaluation versions of the Ethernet MAC cores operate for approximately eight hours in silicon before timing out. To order the full version of the core, visit the Xilinx website at: www.xilinx.com/products/ipcenter/OPB_10_100_Lite.htm Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com...
Page 118: Ucf Location Constraints
• Standard Microsystems SMSC LAN8700 10/100 Ethernet PHY http://www.smsc.com/main/catalog/lan8700.html • Xilinx OPB Ethernet Media Access Controller (EMAC) (v1.04a) www.xilinx.com/support/documentation/ip_documentation/opb_ethernet.pdf • Xilinx OPB Ethernet Lite Media Access Controller (v1.01a) The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for applications the do not require support for interrupts, back-to-back data transfers, and statistics counters.
Page 119 6 differential pairs, high-performance Optionally, 12 single-ended I/O 6-pin Accessory Header, J19 Mounting holes only 6-pin Accessory Header, J20 6-pin Accessory Header, J18 UG334_c15_01_052407 Figure 15-1: Expansion Headers Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 120: Chapter 15: Expansion Connectors
I/O pins. Expansion Connector Compatibility For the majority of applications, the FX2 connector on the Spartan-3A/3AN Starter Kit board is compatible with the other Xilinx development boards. The Spartan-3E Starter Kit board and XC3S1600E Starter Kit board optionally provide limited differential I/O capability on the FX2 connector.
Page 121: Connector Pinout And Fpga Connections
VCCO_012 TMS_B TDO_XC2C JTSEL TCK_B TDO_FX2 FX2_IO1 FX2_IO2 FX2_IO3 FX2_IO4 FX2_IO5 FX2_IO6 FX2_IO7 FX2_IO8 FX2_IO9 FX2_IO10 FX2_IO11 FX2_IO12 FX2_IO13 FX2_IO14 FX2_IO15 FX2_IO16 FX2_IO17 FX2_IO18 FX2_IO19 FX2_IO20 FX2_IO21 FX2_IO22 Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 122: Fx2-Connector Compatible Boards
• Video Decoder Board (VDEC1) from Digilent, Inc. http://www.digilentinc.com/Products/Detail.cfm?Prod=VDEC1 Mating Receptacle Connectors The Spartan-3A/3AN Starter Kit board uses a Hirose FX2-100P-1.27DS header connector. The header mates with any compatible 100-pin receptacle connector, including board- mounted and non-locking cable connectors. •...
Page 123: Ucf Location Constraints
= 8 ; "FX2_IO<40>" = "P20" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; Figure 15-3: UCF Location Constraints for 100-Pin Hirose FX2 Connector Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 124: Differential I/O Connectors
Chapter 15: Expansion Connectors Differential I/O Connectors The Spartan-3A/3AN Starter Kit board includes stake pin headers with excellent signal integrity and matched impedance traces to demonstrate high-performance differential I/O. Each differential pair supports approximately 600 Mbits per second (Mbps) data rates.
Page 125: Using Differential Inputs
The second option, called on-chip differential termination, is highlighted on the Spartan- 3A/3AN Starter Kit board (see Figure 15-4b). This feature uses the DIFF_TERM attribute available on differential I/O signals. Each differential I/O pin includes a circuit that Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 126: Using Differential Outputs
Spartan-3AN FPGAs, differential outputs are only supported on I/O Bank 0 or 2. Differential outputs are powered by the respective I/O bank output voltage, V . On the Spartan-3A/3AN Starter Kit board, I/O Banks 0, 1, and 2 are all powered by a 3.3V supply. FPGA OBUFDS...
Page 127 Bank 2 All traces routed with 100Ω matched impedance. All “transmit” pairs routed with matched trace lengths within 0.25 inches. “Transmit” Header (J15) UG330_c12_15_012407 Figure 15-6: Differential I/O Layout Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 128: 34-Conductor Cable Assemblies (2X17)
IOSTANDARD = LVDS_33 ; "TX_N<4>" = "AB8" IOSTANDARD = LVDS_33 ; "TX_P<4>" = "AA8" IOSTANDARD = LVDS_33 ; Figure 15-7: UCF Location Constraints for “Receive” and “Transmit” Headers www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 129: Six-Pin Accessory Headers
J19 socket on the bottom pin. FPGA J19_IO1 (Y18) J19_IO2 (W18) J19_IO3 (V17) J19_IO4 (W17) 3.3V These pins connect to unpopulated mounting holes. UG334_c15_09_052407 Figure 15-9: FPGA Connections to the J19 Accessory Header Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 130: J20 Header
SPI and other serial protocols. PMODs allow more effective design partitions by routing analog signals and power supplies only where they are needed and away from digital controller boards. • Digilent, Inc. Peripheral Modules http://www.digilentinc.com/Products/Catalog.cfm?Cat=Peripheral www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 131: Ucf Location Constraints
Agilent, provides an interface to a logic analyzer. This debugging port is intended primarily for the Xilinx ChipScope Pro software with the Agilent FPGA Dynamic Probe. It can, however, be used with either the Agilent or Tektronix probes, without the ChipScope software, using FPGA Editor’s probe command.
Page 132 Signal Name FPGA Pin Landing Pads FPGA Pin Signal Name FX2_IO1 FX2_IO2 FX2_IO3 FX2_IO4 FX2_IO5 FX2_IO6 FX2_IO7 FX2_IO8 FX2_IO9 FX2_IO10 FX2_IO11 FX2_IO12 FX2_IO13 FX2_IO14 FX2_IO15 FX2_IO16 FX2_IO17 FX2_IO18 www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...
Page 133: Chapter 16: Miniature Stereo Audio Jack
A monophonic connector will function, but with the following limitations. Only drive signals on the AUD_L signal. Drive the AUD_R output to high-impedance (Hi-Z, three- state) so that it does not compete with the AUD_L channel. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 134: Fpga Connections
= SLOW ; Figure 16-3: UCF Constraints for Audio Connector Related Resources The demonstration design shipped with the board includes an audio example. • Spartan-3A/3AN Starter Kit Demo Design Overview www.xilinx.com/products/boards/s3astarter/reference_designs.htm#demo • Restoring the “Out of the Box” Flash Programming www.xilinx.com/products/boards/s3astarter/reference_designs.htm#out www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide...
Page 135 I/O Banks 0, 1, 2 Supply to FPGA core (VCCINT) UG330_cx_01_021507 Figure 17-1: Spartan-3A/3AN Starter Kit Board Voltage Supplies ® The Spartan -3A/3AN FPGA Starter Kit board requires a 5.0V DC voltage input, typically supplied by the AC wall adapter included with the kit. However, there is also a provision to connect the board directly to a 5.0V DC supply using through-hole mounting solder...
Page 136: Chapter 17: Voltage Supplies
0.9V) VREF inputs (VREF_3) The board exploits all four regulator outputs for testing and evaluation purposes. However, a typical Spartan-3A/3AN FPGA application uses far fewer rails. • The board uses a separate supply for V and sets it to 3.3V by default. In a CCAUX typical application, the FPGA’s V...
Page 137: Measuring Power Across Voltage Supply Jumpers
Set the meter to measure DC Amperes. Initially set the meter to the Ampere range. If appropriate, switch to a lower range (for example, 200 mA) after initially measuring current in the Ampere range. Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 138: I 2 C Voltage Adjustment Interface
(E13) IC19 REG1_SDA REG1-SDA (D13) Possible Applications For experimentation purposes only, Xilinx only recommends adjusting the two supplies listed below: • By default, the V supply to the FPGA is set to 3.3V, as required for Spartan-3AN CCAUX FPGAs. On Spartan-3A FPGAs, V can be either 2.5V or 3.3V, with potentially...
Page 139: Restoring Default Voltages
Related Resources Refer to the following link for additional information: • National Semiconductor LP3906 Dual High-Current Step-Down DC/DC and Dual Linear Regulator with I C Compatible Interface www.national.com/pf/LP/LP3906.html Spartan-3A/3AN FPGA Starter Kit Board User Guidewww.xilinx.com UG334 (v1.1) June 19, 2008...
Page 140 Chapter 17: Voltage Supplies www.xilinx.comSpartan-3A/3AN FPGA Starter Kit Board User Guide UG334 (v1.1) June 19, 2008...

This manual is also suitable for:

Spartan-3an

Xilinx spartan-3a User Manual

Acknowledgments

Guide Contents

Additional Resources

Chapter 1: Introduction and Overview

Getting Started

Operating the Default Demonstration Design

Key Components and Features

Design Trade-Offs

Spartan-3A/3AN FPGA Starter Kit Design Examples

Choose a Spartan-3 Generation Starter Kit Board for Your Needs

Spartan-3A and Spartan-3AN Fpgas

Related Resources

Chapter 2: Switches, Buttons, and Rotary Knob

Slide Switches

SUSPEND Switch

Push-Button Switches

Rotary Push-Button Switch

Discrete Leds

Optional Discrete Leds

Chapter 3: Clock Sources

Overview

Clock Connections

50 Mhz On-Board Oscillator

Auxiliary Clock Oscillator Socket

SMA Clock Input or Output Connector

UCF Constraints

Related Resources

Chapter 4: FPGA Configuration Options

Configuration Mode Jumpers

Xilinx Platform Flash Configuration PROM(S)

PROG Push-Button Switch

DONE Pin LED

Programming the FPGA or Platform Flash PROM Via USB

Chapter 5: Character LCD Screen

Overview

Character LCD Interface Signals

Voltage Compatibility

UCF Location Constraints

LCD Controller

Operation

Related Resources

Chapter 6: VGA Display Port

Signal Timing for a 60 Hz, 640X480 VGA Display

VGA Signal Timing

UCF Location Constraints

Related Resources

Chapter 7: RS-232 Serial Ports

Overview

UCF Location Constraints

Chapter 8: PS/2 Mouse/Keyboard Port

Keyboard

Mouse

Voltage Supply

Adding a Second PS/2 Port Using a Y-Splitter Cable

UCF Location Constraints

Related Resources

Chapter 9: Analog Capture Circuit

Digital Outputs from Analog Inputs

Programmable Pre-Amplifier

Analog-To-Digital Converter (ADC)

Related Resources

Connecting Analog Inputs

Chapter 10: Digital-To-Analog Converter (DAC)

SPI Communication

Specifying the DAC Output Voltage

UCF Location Constraints

Related Resources

Chapter 11: Parallel nor Flash PROM

Flash Connections

UCF Location Constraints

Setting the FPGA Mode Select Pins

Creating and Programming Configuration Images for Parallel Flash

Related Resources

Chapter 12: SPI Serial Flash

SPI Flash PROM Select Jumpers (J1)

UCF Location Constraints

Creating and Programming Configuration Images for SPI Serial Flash

Related Resources

Chapter 13: DDR2 SDRAM