Shared Spi Flash And Platform Flash Data Line - Xilinx Spartan-3A User Manual

Chapter 11: Parallel NOR Flash PROM
Table 11-1: FPGA-to-Flash Connections (Continued)

Shared SPI Flash and Platform Flash Data Line

The least-significant Flash data line, NF_D<0>, is shared with data output signals from the
serial SPI serial Flash PROMs and the serial output from the Platform Flash PROM as
shown in
only one data source is active at any time.
86
NOR Flash
Category Signal Name
NF_BYTE
NF_CE
NF_OE
NF_RP
NF_STS
NF_WE
NF_WP
Table 11-2, page 87. To avoid contention, the FPGA application must ensure that
www.xilinx.com
FPGA Pin
Number
Y21
Active-Low Flash Byte Enable. Connects to
FPGA pin LDC2 to support the BPI
configuration.
0: x8 data
1: x16 data
W20 Active-Low Flash Chip Enable. Connects to
FPGA pin LDC0 to support the BPI
configuration.
0: Enabled
1: Disabled
W19 Active-Low Flash Chip Enable. Connects to
FPGA pin LDC1 to support the BPI
configuration.
0: Enable data outputs to read Flash data
1: Disabled
R22 Active-Low Flash Reset. Connects to FPGA
user-I/O pin.
0: Reset
1: Flash active
P22 Flash Status signal. Optional input to FPGA
open-drain output from Flash.
AA22 Active-Low Flash Write Enable. Connects to
FPGA pin HDC to support the BPI
configuration.
0: Enable Flash data write operations
1: Disabled
E14 Active-Low Hardware Write Protect. Connects
to FPGA user-I/O pin.
0: Protect two outermost Flash boot blocks
against all program and erase operations.
1: Hardware protection disabled.
Spartan-3A/3AN Starter Kit Board User Guide
Function
UG334 (v1.0) May 28, 2007
R