Communication Protocol - Xilinx Spartan-3A User Manual

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After driving the DAC_CS slave select signal Low, the FPGA transmits data on the
SPI_MOSI signal, MSB first. The LTC2624 captures input data (SPI_MOSI) on the rising
edge of SPI_SCK; the data must be valid for at least 4 ns relative to the rising clock edge.
The LTC2624 DAC transmits its data on the DAC_OUT signal on the falling edge of
SPI_SCK. The FPGA captures this data on the next rising SPI_SCK edge. The FPGA must
read the first DAC_OUT value on the first rising SPI_SCK edge after DAC_CS goes Low.
Otherwise, bit 31 is missed.
After transmitting all 32 data bits, the FPGA completes the SPI bus transaction by
returning the DAC_CS slave select signal High. The High-going edge starts the actual
digital-to-analog conversion process within the DAC.

Communication Protocol

Figure 10-4
DAC. The DAC supports both 24-bit and 32-bit protocol. The 32-bit protocol is shown.
Inside the DAC, the SPI interface is formed by a 32-bit shift register. Each 32-bit command
word consists of a command and an address, followed by a data value. As a new command
enters the DAC, the previous 32-bit command word is echoed back to the master. The
response from the DAC can be ignored although it is a useful to confirm correct
communication.
DAC_OUT
SPI_MOSI
DAC_CS
Master
SPI_SCK
FPGA
Figure 10-4: SPI Communications Protocol to LTC2624 DAC
Spartan-3A/3AN Starter Kit Board User Guide
UG334 (v1.0) May 28, 2007
DAC _CS
31
SPI_MOSI
SPI_SCK
DAC _OUT Previous 31
Figure 10-3: SPI Communication Waveforms
shows the communications protocol required to interface with the LTC2624
0 Slave: LTC2624 DAC
x x x x
0 1 2 3 4 5 6
lsb
Don't Care
12-bit Unsigned
DATA
a a
3 2
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
1 1 1 1
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30
Previous 30
a a a a c
7 8 9 10 11
0 1 2 3 0
msb
COMMAND
ADDRESS
a a
1 0
DAC A
DAC B
DAC C
DAC D
All
SPI Communication
29
Previous 29
UG330_c9_03 _ 071906
3 1
c x x x x x x x x
c c
1
2 3
Don't Care
UG334_c10_04_052407
81