Fpga Connections; Ucf Location Constraints; Related Resources - Xilinx Spartan-3A User Manual

Chapter 16: Miniature Stereo Audio Jack

FPGA Connections

The FPGA drives a 3.3V digital signal to each side of the audio jack, as indicated in
Table
Table 16-1: Digital Outputs to Stereo Minijack

UCF Location Constraints

Figure 16-3

Related Resources

The demonstration design shipped with the board includes an audio example.
•
•
136
2.5 mm
Monophonic
(one insulator band)
(left channel only)
Figure 16-2: Examples of Miniature Stereo Jacks
16-1. A monophonic connector only uses the left-side channel
Signal Name
AUD_L
AUD_R
provides the UCF constraints for the audio connector.
# Controls VCCAUX supply rail (IC19)
NET "AUD_L" LOC = "Y10" |
NET "AUD_R" LOC = "V10" |
Figure 16-3: UCF Constraints for Audio Connector
Spartan-3A/3AN Starter Kit Demo Design Overview
www.xilinx.com/products/boards/s3astarter/reference_designs.htm#demo
Restoring the "Out of the Box" Flash Programming
www.xilinx.com/products/boards/s3astarter/reference_designs.htm#out
www.xilinx.com
1/8"
1/4"
(3.5 mm)
(6.3 mm)
Stereophonic
(two insulator bands)
FPGA Pins Stereo Jack
Y10 Left-side audio
V10 Right-side audio
IOSTANDARD = LVTTL | DRIVE
IOSTANDARD = LVTTL | DRIVE
Spartan-3A/3AN Starter Kit Board User Guide
UG330_c16_02_021507
Mono Jack
Audio channel
Drive to Hi-Z
= 8 | SLEW = QUIETIO ;
= 8 | SLEW = QUIETIO ;
UG334 (v1.0) May 28, 2007
R