Interface Signals; Spi Communication Details - Xilinx Spartan-3A User Manual

Chapter 10: Digital-to-Analog Converter (DAC)

Interface Signals

Table 10-1
DAC_OUT, and SPI_SCK signals are shared with other devices on the SPI bus. The
DAC_CS signal is the active-Low slave select input to the DAC. The DAC_CLR signal is
the active-Low, asynchronous reset input to the DAC.
Table 10-1: DAC Interface Signals
The serial data output from the DAC is primarily used to cascade multiple DACs. This
signal can be ignored in most applications although it does demonstrate full-duplex
communication over the SPI bus.

SPI Communication Details

Figure 10-3
received relative to the SPI_SCK clock signal. The bus is fully static and supports clock
rates up to the maximum of 50 MHz. However, check all timing parameters using the
LTC2624 data sheet if operating at or close to the maximum speed.
80
3.3V
3.3V by default.
Programmable reference
supplied by adjustable
LP3906 regulator, IC18.
FPGA
SPI_MOSI
(V7) (AB14)
DAC_CS
(W7)
SPI_SCK
(AA20)
DAC_CLR
(AB13)
DAC_OUT
Figure 10-2: Digital-to-Analog Connection Schematics
lists the interface signals between the FPGA and the DAC. The SPI_MOSI,
Signal FPGA Pin
SPI_MOSI AB14
DAC_CS W7
SPI_SCK AA20
DAC_CLR AB13
DAC_OUT V7
shows a detailed example of the SPI bus timing. Each bit is transmitted or
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LTC 2624 DAC
REF A
DAC A
12
REF B
DAC B
12
REF C
DAC C
12
REF D
DAC D
12
SDI
CS/LD
SPI Control Interface
SCK
CLR
Direction
FPGA DAC Serial data: Master Output, Slave Input
FPGA DAC Active-Low chip-select. Digital-to-analog
conversion starts when this signal returns
High.
FPGA DAC Clock
FPGA DAC Asynchronous, active-Low reset input
FPGA DAC Serial data from the DAC
Spartan-3A/3AN Starter Kit Board User Guide
Header J5
VOUTA
A
VOUTB
B
VOUTC
C
VOUTD
D
GND
SDO
VCC
(3.3V)
UG334_c10_02_052407
Description
UG334 (v1.0) May 28, 2007
R