Awake Led; Init_B Led; Ucf Location Constraints - Xilinx Spartan-3A User Manual

Chapter 2: Switches, Buttons, and Rotary Knob

AWAKE LED

The yellow-colored AWAKE LED connects to the FPGA's AWAKE pin and is used if the
FPGA Suspend mode is enabled in the bitstream. If the Suspend mode is not used, then the
FPGA's AWAKE pin is available as a full user-I/O pin.
If the FPGA is not yet configured, the FPGA's AWAKE pin is dimly lit because pull-up
resistors are enabled during configuration. The FPGA's PUDC_B pin is connected to GND
on the board.
To light the AWAKE LED in an application, drive the AWAKE pin High.

INIT_B LED

The red-colored INIT_B LED serves multiple purposes:
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If using the INIT_B pin as a user-I/O pin after configuration, drive the pin Low to light the
LED and High to shut it off. Jumper J46, shown in
"Disabled" or "Enabled during Configuration" setting.
The "Always Enabled" setting for Jumper J46 allows the FPGA to read additional data
from the Platform Flash PROM after configuration, as described in Xilinx application note
XAPP694.
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UCF Location Constraints

Figure 2-15
assignment, the I/O standard used, the output slew rate, and the output drive current. The
ENABLE_SUSPEND constraint must be set to NO in order to use FPGA_AWAKE LED.
32
At power-up or when the PROG_B button is pressed, the LED flashes momentarily
while the FPGA clears its configuration memory.
If configuration fails for any reason, then the FPGA's DONE LED will be unlit and the
INIT_B LED will light. This indicates that the FPGA could not successfully configure.
After the FPGA successfully completes, the INIT_B pin is available as a general-
purpose user-I/O pin. If no signal drives INIT_B, then it is defined as an input pin
with a pull-down resistor. It might appear that the LED dimly glows. Drive the
INIT_B pin High to turn off the LED or Low to light the LED.
If using the Readback CRC feature, the INIT_B pin is reserved and signals a CRC error
after configuration. If such an error occurs, the FPGA drives INIT_B Low, lighting the
LED.
Caution!
The FPGA's INIT_B pin also connects to the Platform Flash PROM's OE/RESET pin.
If the jumper controlling the Platform Flash PROM, jumper J46 in
"Always Enabled," then the INIT_B signal controls the PROM's active-Low output-enable (OE)
input or active-High RESET input.
XAPP694: Reading User Data from Configuration PROMs
www.xilinx.com/bvdocs/appnotes/xapp694.pdf
provides the UCF constraints for the optional LEDs, including the I/O pin
NET "FPGA_INIT_B" LOC = "V13" |
# The AWAKE LED is only available if Suspend mode is disabled
CONFIG ENABLE_SUSPEND = NO ;
NET "FPGA_AWAKE" LOC = "AB15" |
Figure 2-15: UCF Constraints for Optional Discrete LEDs
www.xilinx.com
Table 4-2, page
IOSTANDARD = LVTTL | SLEW
IOSTANDARD = LVTTL | SLEW
Spartan-3A/3AN Starter Kit Board User Guide
40, must be in either the
Table 4-2, page 40, is set to
= QUIETIO | DRIVE = 4 ;
= QUIETIO | DRIVE = 4 ;
UG334 (v1.0) May 28, 2007
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