Ucf Location Constraints; Analog-To-Digital Converter (Adc); Interface; Spi Control Interface - Xilinx Spartan-3A User Manual

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UCF Location Constraints

Figure 9-5
including the I/O pin assignment and I/O standard used.

Analog-to-Digital Converter (ADC)

The LTC1407A-1 provides two ADCs. Both analog inputs are sampled simultaneously
when the AD_CONV signal is applied.

Interface

Table 9-3
shared with other devices on the SPI bus. The active-High AD_CONV signal is the active-
Low slave select input to the DAC. The DAC_CLR signal is the active-Low, asynchronous
reset input to the DAC.
Table 9-3: ADC Interface Signals

SPI Control Interface

Figure 9-6
When the AD_CONV signal goes High, the ADC simultaneously samples both analog
channels. The results of this conversion are not presented until the next time AD_CONV is
asserted, a latency of one sample. The maximum sample rate is approximately 1.5 MHz.
The ADC presents the digital representation of the sampled analog values as a 14-bit, two's
complement binary value.
Spartan-3A/3AN Starter Kit Board User Guide
UG334 (v1.0) May 28, 2007
provides the User Constraint File (UCF) constraints for the amplifier interface,
NET "SPI_MOSI" LOC = "AB14"|
NET "AMP_CS" LOC = "W6"
NET "SPI_SCK" LOC = "AA20"|
NET "AMP_SHDN" LOC = "W15" |
NET "AMP_DOUT" LOC = "T7"
Figure 9-5: UCF Location Constraints for the Pre-amplifier Interface (AMP)
lists the interface signals between the FPGA and the ADC. The SPI_SCK signal is
Signal FPGA Pin
SPI_SCK AA20 FPGA ADC Clock
AD_CONV Y6 FPGA ADC Active-High, initiates conversion process.
ADC_OUT D16 FPGA ADC Serial data. Presents the digital representation of the
provides an example SPI bus transaction to the ADC.
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IOSTANDARD = LVTTL |
| IOSTANDARD = LVTTL |
IOSTANDARD = LVTTL |
IOSTANDARD = LVTTL |
| IOSTANDARD = LVTTL ;
Direction
sample analog values as two 14-bit two's
complement binary values.
Analog-to-Digital Converter (ADC)
SLEW = SLOW | DRIVE
SLEW = SLOW | DRIVE
SLEW = SLOW | DRIVE
SLEW = SLOW | DRIVE
Description
= 8 ;
= 4 ;
= 12 ;
= 4 ;
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