Xilinx Spartan-3A User Manual page 138

Starter kit board
Hide thumbs Also See for Spartan-3A:
Table of Contents

Advertisement

Chapter 17: Voltage Supplies
regulators. Each regulator incorporates two high-current switching (buck) regulators and
two low-drop out (LDO) linear regulators.
Table 17-1: Voltage Regulators and Supply Rails
The board exploits all four regulator outputs for testing and evaluation purposes.
However, a typical Spartan-3A/3AN FPGA application uses far fewer rails.
138
Voltage
Regulator
Regulator
Output
SW1
National
SW2
Semiconductor
LP3906
(IC19)
LDO1
LDO2
SW1
SW2
National
Semiconductor
LP3906
LDO1
(IC18)
LDO2
The board uses a separate supply for V
typical application, the FPGA's V
supply used for FPGA I/O Banks 0, 1, and 2.
By default, the V
CCAUX
2
Using the I
C interface on regulator IC19, V
reduce overall power consumption or to verify operation with V
The DDR2 SDRAM interface uses multiple regulator outputs to test voltage
margining.
One high-current 1.8V rail supports the DDR2 SDRAM component itself, and
supplies the FPGA's I/O Bank 3, which connects to the DDR2 SDRAM.
One high-current 0.9V supplies the DDR2 SDRAM termination network.
A low-current 1.8V supply is voltage divided with resistors to provide a high-
accuracy 0.9V voltage reference for the DDR2 SDRAM component and to supply
the VREF inputs on FPGA I/O Bank 3.
See
Chapter 13, "DDR2 SDRAM"
www.xilinx.com
Series
Voltage Level
Jumper
Control
1.2V
J9
3.3V
J10
3.3V
J11
1.8V
J12
0.9V
J40
1.8V
J13
3.3V
J41
1.8V
(voltage divided
J42
to 0.9V)
and sets it to 3.3V by default. In a
CCAUX
supply could connect directly to the 3.3V
CCAUX
supply is set to 3.3V
CCAUX
for additional information.
Spartan-3A/3AN Starter Kit Board User Guide
Components Supplied
FPGA internal core voltage,
V
CCINT
FPGA I/O Banks 0, 1, and 2
(VCCO_0, VCCO_1, and
VCCO_2). All 3.3V
components.
FPGA internal auxiliary
voltage, V
CCAUX
Embedded USB programmer
DDR2 SDRAM termination
network
DDR2 SDRAM component,
FPGA I/O Bank 3 (VCCO_3)
Voltage reference to D/A
converter channels C and D.
DDR2 SDRAM voltage
reference, FPGA I/O Bank 3
VREF inputs (VREF_3)
can be reduced to 2.5V to
= 2.5V.
CCAUX
UG334 (v1.0) May 28, 2007
R

Advertisement

Table of Contents
loading

This manual is also suitable for:

Spartan-3an

Table of Contents