Ucf Location Constraints - Xilinx Spartan-3A User Manual

Chapter 7: RS-232 Serial Ports
Figure 7-1
FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim device,
which in turn, converts the logic value to the appropriate RS-232 voltage level. Likewise,
the Maxim device converts the RS-232 serial input data to LVTTL levels for the FPGA. A
series resistor between the Maxim output pin and the FPGA's RXD pin protects against
inadvertent logic conflicts such as accidentally connecting the board using a null-modem
cable. In this example, both the FPGA and the external serial device are driving data on the
transmit line.
Hardware flow control is not supported on the connector. The port's DCD, DTR, and DSR
signals connect together, as shown in
connect together.

UCF Location Constraints

Figure 7-2
respectively, including the I/O pin assignment and the I/O standard used.
64
shows the connection between the FPGA and the two DB9 connectors. The
and Figure 7-3 provide the UCF constraints for the DTE and DCE RS-232 ports,
NET "RS232_DTE_RXD" LOC
NET "RS232_DTE_TXD" LOC
Figure 7-2: UCF Location Constraints for DTE RS-232 Serial Port
NET "RS232_DCE_RXD" LOC
NET "RS232_DCE_TXD" LOC
Figure 7-3: UCF Location Constraints for DCE RS-232 Serial Port
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Figure 7-1. Similarly, the port's RTS and CTS signals
= "F16" | IOSTANDARD = LVTTL ;
= "E15" | IOSTANDARD = LVTTL |
= "E16" | IOSTANDARD = LVTTL ;
= "F15" | IOSTANDARD = LVTTL |
Spartan-3A/3AN Starter Kit Board User Guide
DRIVE = 4 | SLEW = SLOW ;
DRIVE = 4 | SLEW = SLOW ;
UG334 (v1.0) May 28, 2007
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