Using Differential Inputs - Xilinx Spartan-3A User Manual

R
Table 15-4
association, the FPGA ball assignment, and the connecting header pin.
Table 15-4: Differential I/O Connections and Header Connections
Differential Pair Signal Name
"Receive" Header, J2 (Top Header)
RX_<0>
RX_<1>
RX_<2>
RX_<3>
RX_<4>
RX_CLK_N
RX_CLK
RX_CLK_P
"Transmit" Header J15 (Bottom Header)
TX_<0>
TX_<1>
TX_<2>
TX_<3>
TX_<4>
TX_CLK_N
TX_CLK
TX_CLK_P

Using Differential Inputs

LVDS and RSDS differential inputs require input termination. Two options are generally
available. The first option is to use external termination resistors, as shown in
External input termination resistors are not provided on the differential I/O pins.
The second option, called on-chip differential termination, is highlighted on the Spartan-
3A/3AN Starter Kit board (see
available on differential I/O signals. Each differential I/O pin includes a circuit that
Spartan-3A/3AN Starter Kit Board User Guide
UG334 (v1.0) May 28, 2007
provides further detail on the pin assignment, including the differential pair
FPGA Ball
RXN_<0> B4
RXP_<0> A4
RXN_<1> A5
RXP_<1> B6
RXN_<2> A6
RXP_<2> A7
RXN_<3> A8
RXP_<3> A9
RXN_<4> C10
RXP_<4> A10
A11
A12
TXN_<0> AA3
TXP_<0> AB2
TXN_<1> AA4
TXP_<1> AB3
TXN_<2> AB6
TXP_<2> AA6
TXN_<3> AB7
TXP_<3> Y7
TXN_<4> AB8
TXP_<4> AA8
AB10
AA10
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FPGA Pin Name Signal Direction
IO_L31N_0
IO_L31P_0
IO_L28N_0
IO_L28P_0
IO_L26N_0
IO_L26P_0
IO_L22N_0
IO_L22P_0
IO_L21N_0
IO_L21P_0
IO_L18N_0
GLK7
IO_L18P_0
GCLK8
IO_L03N_2
IO_L03P_2
IO_L04N_2
IO_L04P_2
IO_L08N_2
IO_L08P_2
IO_L10N_2
IO_L10P_2
IO_L12N_2
IO_L12P_2
IO_L15N_2
IO_L15P_2
Figure 15-4b). This feature uses the DIFF_TERM attribute
Differential I/O Connectors
Header.Pin
I/O J2.6
I/O J2.5
I/O J2.10
I/O J2.9
I/O J2.14
I/O J2.13
I/O J2.22
I/O J2.21
I/O J2.26
I/O J2.25
I/O J2.30
I/O J2.29
I/O J1..6
I/O J1.5
I/O J1.10
I/O J1.9
I/O J1.14
I/O J1.13
I/O J1.22
I/O J1.21
I/O J1.26
I/O J1.25
I/O J1.30
I/O J1.29
Figure 15-4a.
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