Ldc (Load To Control Register) - Hitachi H8/300L Series Programming Manual

2.2.31 LDC (load to control register)

Operation
(EAs) → CCR
Assembly-Language Format
LDC <EAs>, CCR
Operand Size
Byte
Condition Code
I H
∆ ∆ ∆ ∆
I: Loaded from the source operand.
H: Loaded from the source operand.
N: Loaded from the source operand.
Z: Loaded from the source operand.
V: Loaded from the source operand.
C: Loaded from the source operand.
Description
This instruction loads the source operand contents into the condition code register (CCR). Bits 4
and 6 are loaded as well as the flag bits.
No interrupt requests are accepted immediately after this instruction. All interrupts are deferred
until after the next instruction.
Instruction Formats and Number of Execution States
Addressing
mode Mnem.
Immediate LDC
Register direct LDC
88
N Z V C
∆ ∆ ∆ ∆
Instruction code
Operands 1st byte
#xx:8, CCR 0 7
Rs, CCR 0 3
2nd byte 3rd byte 4th byte
IMM
0 rs
No. of
states
2
2