Shlr (Shift Logical Right) - Hitachi H8/300L Series Programming Manual

2.2.50 SHLR (shift logical right)

Operation
Rd (shifted logical right) → Rd
Assembly-Language Format
SHLR Rd
Operand Size
Byte
Condition Code
I H
— — — —
I: Previous value remains unchanged.
H: Previous value remains unchanged.
N: Set to 1 when the result is negative; otherwise cleared to 0.
Z: Set to 1 when the result is zero; otherwise cleared to 0.
V: Cleared to 0.
C: Receives the previous value in bit 0.
Description
This instruction shifts an 8-bit general register one bit to the right. The most significant bit is
cleared to 0. The least significant bit shifts into the carry flag.
The operation is shown schematically below.
MSB
0
Bit 7
N Z V C
∆ ∆
—
0
LSB
Bit 0 C
117