Hitachi H8/300L Series Programming Manual page 39

Assembly-Language Format:
The assembly-language coding of the instruction is given. An example is:
ADD. B <EAs>, Rd
Mnemonic Size
The operand size is indicated by the letter B (byte) or W (word). Some instructions have
restrictions on the size of operands they handle.
The abbreviation EAs or EAd (effective address of source or destination) is used for operands
that permit more than one addressing mode. The H8/300L CPU supports the following eight
addressing modes. The method of calculating effective addresses is explained in section 1.3.4,
Addressing Modes and Effective Address Calculation, above.
Notation Addressing Mode
Rn Register direct
@Rn Register indirect
@(d: 16, Rn) Register indirect with displacement
@Rn+/@ -Rn Register indirect with post-increment/pre-decrement
@aa:8/@aa:16 Absolute address
#xx:8/#xx:16 Immediate
@(d:8, PC) Program-counter relative
@@aa:8 Memory indirect
Operand size: Word or byte. Byte size is indicated for bit-manipulation instructions because
these instructions access a full byte in order to read or write one bit.
Condition code: The effect of instruction execution on the flag bits in CCR is indicated. The
following notation is used:
Symbol Meaning
∆
The flag is altered according to the result of the instruction.
0 The flag is cleared to "0."
−
The flag is not changed.
* Not fixed; the flag is left in an unpredictable state.
Description: The action of the instruction is described in detail.
Instruction Formats: Each possible format of the instruction is shown explicitly, indicating the
addressing mode, the object code, and the number of states required for execution when the
Source Destination
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