Hitachi H8/300L Series Programming Manual page 87

Instruction Formats and Number of Execution States
Addressing
mode Mnem.
Register direct DIVXU
Note: DIVXU Overflow
Since the DIVXU instruction performs 16-bit ÷ 8-bit → 8-bit division, an overflow will occur if
the divisor byte is equal to or less than the upper byte of the dividend. For example, H'FFFF ÷
H'01 → H'FFFF causes an overflow. (The quotient has more than 8 bits.)
Overflows can be avoided by using a subprogram like the following. A work register is required.
To perform
DIVXU R0L, R1:
MOV.B #H'00, R2H
CMP.B R0L, R1H
BCC L1
DIVXU R0L, R1
MOV.B R1L, R2L
BRA L2
L1 MOV.B R1H, R2L
DIVXU R0L, R2
MOV.B R2H, R1H
DIVXU R0L, R1
MOV.B R2L, R2H
MOV.B R1L, R2L
L2 RTS (*4)
Instruction code
Operands 1st byte
Rs, Rd 5 1
(*1)
(*2)
(*3)
2nd byte 3rd byte 4th byte
rs 0 rd
No. of
states
14
81