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2.2.57 XORC (exclusive OR control register)
Operation
CCR ⊕ #IMM → CCR
Assembly-Language Format
XORC #xx:8, CCR
Operand Size
Byte
Condition Code
I
H
∆
∆
∆
∆
I:
Exclusive-ORed with bit 7 of the immediate data.
H:
Exclusive-ORed with bit 5 of the immediate data.
N:
Exclusive-ORed with bit 3 of the immediate data.
Z:
Exclusive-ORed with bit 2 of the immediate data.
V:
Exclusive-ORed with bit 1 of the immediate data.
C:
Exclusive-ORed with bit 0 of the immediate data.
Description
This instruction exclusive-ORs the condition code register (CCR) with immediate data and
places the result in the condition code register. Bits 6 and 4 are exclusive-ORed as well as the
flag bits.
No interrupt requests are accepted immediately after this instruction. All interrupts, including
the nonmaskable interrupt (NMI), are deferred until after the next instruction.
Instruction Formats and Number of Execution States
Addressing
mode
Mnem.
Immediate
XORC
N
Z
V
C
∆
∆
∆
∆
Instruction code
Operands
1st byte
#xx:8, CCR 0
5
2nd byte
3rd byte
IMM
No. of
4th byte
states
2
127
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