Table Of Contents - Hitachi H8/300L Series Programming Manual

Preface ....... .....................................................................................................1
Section 1. CPU.................................................................................................3
1.1 Overview ......................................................................................................................... 3
1.1.1 Features .............................................................................................................. 3
1.1.2 Data Structure..................................................................................................... 4
1.1.3 Address Space..................................................................................................... 6
1.1.4 Register Configuration........................................................................................ 6
1.2 Registers .......................................................................................................................... 7
1.2.1 General Registers................................................................................................ 7
1.2.2 Control Registers ................................................................................................ 7
1.2.3 Initial Register Values ........................................................................................ 8
1.3 Instructions ...................................................................................................................... 9
1.3.1 Types of Instructions........................................................................................... 9
1.3.2 Instruction Functions .......................................................................................... 9
1.3.3 Basic Instruction Formats ................................................................................... 20
1.3.4 Addressing Modes and Effective Address Calculation ........................................ 25
Section 2. Instruction Set..................................................................................31
2.1 Explanation Format.......................................................................................................... 31
ADD (add binary) (byte).............................................................................................. 31
2.2 Instructions ...................................................................................................................... 36
2.2.1(1) ADD (add binary) (byte) ................................................................................ 36
2.2.1 (2) ADD (add binary) (word) .............................................................................. 37
2.2.2 ADDS (add with sign extension)......................................................................... 38
2.2.3 ADDX (add with extend carry) ........................................................................... 39
2.2.4 AND (AND logical)............................................................................................ 40
2.2.5 ANDC (AND control register) ............................................................................ 41
2.2.6 BAND (bit AND)................................................................................................ 42
2.2.7 Bcc (branch conditionally).................................................................................. 44
2.2.8 BCLR (bit clear) ................................................................................................. 47
2.2.9 BIAND (bit invert AND) .................................................................................... 49
2.2.10 BILD (bit invert load) ....................................................................................... 51
2.2.11 BIOR (bit invert inclusive OR) ......................................................................... 53
2.2.12 BIST (bit invert store)....................................................................................... 55
2.2.13 BIXOR (bit invert exclusive OR) ...................................................................... 57
2.2.14 BLD (bit load) .................................................................................................. 59
2.2.15 BNOT (bit NOT) .............................................................................................. 61
2.2.16 BOR (bit inclusive OR)..................................................................................... 63
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