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the instruction or an operand is located in external memory or the on-chip register field,
additional states are required for each access. See section 2.5, Number of Execution States.
2.2 Instructions
2.2.1(1) ADD (add binary) (byte)
Operation
Rd+ (EAs) → Rd
Assembly-Language Format
ADD.B <EAs>, Rd
Operand Size
Byte
Condition Code
I
H
∆
— —
—
I:
Previous value remains unchanged.
H:
Set to 1 when there is a carry from bit 3; otherwise cleared to 0.
N:
Set to 1 when the result is negative; otherwise cleared to 0.
Z:
Set to 1 when the result is zero; otherwise cleared to 0.
V:
Set to 1 when an overflow occurs; otherwise cleared to 0.
C:
Set to 1 when there is a carry from bit 7; otherwise cleared to 0.
Description
This instruction adds the source operand to the contents of an 8-bit general register and places
the result in the general register.
Instruction Formats and Number of Execution States
Addressing
mode
Mnem.
Immediate
ADD.B
Register direct ADD B
36
N
Z
V
C
∆
∆
∆
∆
Instruction code
Operands
1st byte
#xx:8, Rd
8
rd
Rs, Rd
0
8
2nd byte
3rd byte
IMM
rs
rd
No. of
4th byte
states
2
2
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