SBC PCD1 Series Manual page 253

Saia-Burgess Controls AG
Block diagram
Clock
CLK
/Clock
/CLK
Data D
/Data
/D
Output 12
A 12
Output 13
A 13
Output 14 A 14
Output 15 A 15
For further details, please refer to manual 26/761 "PCD2.H150 - SSI interface for
absolute encoder".
Watchdog: This module cannot be used on the base address 240 (or 496 for the
PCD2.M17x), because it would interact with the watchdog, and would cause a
malfunction.
For details, please refer to the
the watchdog in conjunction with PCD2 components.
Manual Manual PCD 1 / PCD 2 Series │ D ocument 26 / 737 EN22 │ 2 013-11-26
User PROM
FPGA
(Field Programmable
Gate Array)
Input filter and adaptation 24V to 5V
Output amplifier 5 .to. 32 V
"Watchdog" section, which describes the correct use of
Input/output (I/O) modules
(Uext)
DC
SSI interface modules
5-117
5