System Architecture
SPORT0 Interface
connects to the audio circuit,
SPORT0
sion interface. The audio circuit uses the primary data transmit and
receive pins to input and output data from the audio input and outputs.
and
SPORT1
SPORT2
and
) and expansion interface.
P4
The pinout of the SPORT interface and expansion interface connectors
can be found in
SPI Interface
The serial peripheral interface (SPI) of the processor connects to the SPI
connectors (
P1
UART Interface
The UART interface of the processor connects to the UART connectors
(
,
, and
P12
P14
Programmable Flags
The processor has 53 general-purpose input/output (GPIO) signals spread
across four ports (
depend on the processor setup.
flag pins are used on the EZ-KIT Lite.
Table 2-1. Programmable Flag Connections
Processor Pin
PC0
PC1
2-4
of the processor connect to the
"ADSP-BF538F EZ-KIT Lite Schematic" on page
,
, and
) and expansion interface.
P2
P9
) and expansion interface.
P15
,
,
, and
PC
PD
PE
Table 2-1
Other Processor Function
CANTX
CANRX
ADSP-BF538F EZ-KIT Lite Evaluation System Manual
connector (
SPORT0
SPORT
). The pins are multi-functional and
PF
shows how the programmable
EZ-KIT Lite Function
UART0
CTS/CAN
UART0
CTS/CAN
), and expan-
P6
connectors (
P3
B-1.
transmit
receive
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