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S1R72105 Technical Manual
7.5.2.13 EPr FIFO Control (EPrFIFOCtrl) R/W
Checks the status and sets operation of FIFO of the endpoint.
USBIndex : 01h to 03h
Address
Register Name
1Fh
EPrFIFOCtrl
BIT7 FIFO Empty
When this bit is HIGH it indicates that FIFO is empty.
If a reading operation of FIFO is carried out in this state, invalid data is read out.
BIT6 FIFO Full
When this bit is HIGH it indicates that FIFO is full.
If a writing operation into FIFO is carried out in this state, the data is ignored.
BIT5 FIFO Clear
Setting this bit to HIGH clears data stored in FIFO.
The bit returns to LOW automatically after clearing.
BIT2 AutoForceNAK
Setting this bit to HIGH sets the InForceNAK bit of the EP0InControl register and the OutForceNAK bit of the
EP0OutControl register when transaction is completed normally.
BIT1 Enable FIFO Write
Setting this bit to HIGH enables writing data into FIFO from the CPU.
BIT0 Enable FIFO Read
Setting this bit to HIGH enables reading data in FIFO from the CPU.
7.5.2.14 EP0 SETUP [n](n=0,1,2,3,4,5,6,7) (EP0SETUP[n]) R
Displays data received in the SETUP stage.
USBIndex : 08h
Address
Register Name
18h to 1Fh Ep0SETUP[0]
Ep0SETUP[7]
50
Bit Symbol
7: FIFOEmpty
6: FIFOFull
5: FIFOClr
4: 0
3: 0
2: AutoForceNAK
1: EnFIFOwr
0: EnFIFOrd
Bit Symbol
7: Ep0_RcvSETUPdata[7]
6: Ep0_RcvSETUPdata[6]
5: Ep0_RcvSETUPdata[5]
4: Ep0_RcvSETUPdata[4]
3: Ep0_RcvSETUPdata[3]
2: Ep0_RcvSETUPdata[2]
1: Ep0_RcvSETUPdata[1]
0: Ep0_RcvSETUPdata[0]
EPSON
Description
FIFO Empty
FIFO Full
FIFO Clear
Reserved
Reserved
AutoForceNAK
Enable FIFO Write
Enable FIFO Read
Description
Ep0_RcvSETUPdata
Rev.1.0
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