Ep0 Fifo Control(Ep0Fifoctrl) R/W - Epson S1R72105 Technical Manual

S1R72105 Technical Manual
7.5.2.7 EP0 FIFO Control (EP0FIFOCtrl) R/W
Checks the status and sets operation of FIFO of Endpoint 0.
USBIndex : 00h
Address Register Name
1Fh EP0FIFOCtrl
BIT7 FIFO Empty
When this bit is HIGH it indicates that FIFO is empty.
If a reading operation of FIFO is carried out in this state, invalid data is read out.
BIT6 FIFO Full
When this bit is HIGH it indicates that FIFO is full.
If a writing operation into FIFO is carried out in this state, the data is ignored.
BIT5 FIFO Clear
Setting this bit to HIGH clears data stored in FIFO.
The bit returns to LOW automatically after clearing.
BIT4 ALL FIFO Clear
Setting this bit to HIGH clears FIFO of all Endpoints.
When the MaxPacketSize filed or DoubleBuf bit of each Endpoint is set, be sure to set this bit to HIGH once after
completion of setting.
The bit returns to LOW automatically after clearing FIFO.
BIT2 AutoForceNAK
Setting this bit to HIGH sets the InForceNAK bit of the EP0InControl register and the OutForceNAK bit of the
EP0OutControl register when transaction is completed normally.
BIT1 Enable FIFO Write
Setting this bit to HIGH enables writing data into FIFO from the CPU.
BIT0 Enable FIFO Read
Setting this bit to HIGH enables reading data in FIFO from the CPU.
46
Bit Symbol
7: FIFOEmpty
6: FIFOFull
5: FIFOClr
4: ALLFIFOClr
3: 0
2: AutoForceNAK
1: EnFIFOwr
0: EnFIFOrd
EPSON
Description
FIFO Empty
FIFO Full
FIFO Clear
ALL FIFO Clear
Reserved
AutoForceNAK
Enable FIFO Write
Enable FIFO Read
Rev.1.0