Ep{R}(R=0,A,B,C) Interrupt Enable(Ep{R}Intenb) R/W - Epson S1R72105 Technical Manual

S1R72105 Technical Manual
7.4.3 EP {r} (r=0,a,b,c) Interrupt Enable (EP {r} IntEnb) R/W
Appears in IntEnbWindow 0,1. This register enables/disables endpoint interruption shown in
IntStatWindow_0,1.
When the corresponding bit is set to HIGH an interruption to the CPU is enabled.
IntIndex_n: 0h to 3h
Address Register Name
07h,08h EP0IntStat, EPaIntStat
EPbIntStat ,EPcIntStat
40
Bit Symbol
7: EnINtranACK
6: EnOUTtranCmp
5: EnINtranErr
4: EnOUTtranErr
3: EnINtranNAK
2: EnOUTtranNAK
1: EnINtokenRcv
0: EnOUTtokenRcv
EPSON
Description
Enable IN Transaction ACK
Enable OUT Transaction Complete
Enable IN Transaction Error
Enable OUT Transaction Error
Enable IN Transaction NAK
Enable OUT Transaction NAK
Enable IN Token Received
Enable OUT Token Received
Rev.1.0