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S1R72105 Technical Manual
7.3.31 SCSI Mode Select0 (SCSIMODE0) R/W
Sets operation related to the SCSI interface.
Address
Register Name
29h
SCSIMODE0
BIT4 ULTRA SCSI
When this bit is HIGH, the ULTRA-SCSI transfer is enabled.
SYNCMODE register is set at "0" or "1".
BIT3 AUTO1 (auto status)
Automatically executes STS_MSG→Busfree→Wait_SEL_CMD after executing the DMA_DATA_IN/OUT
command.
At the end of execution, ASCMP interrupt occurs. The bit setting is also valid in FIFO-DMA mode.
BIT2 AUTO2 (status message stop)
Executes automatically STS_MSG after executing the DMA_DATA_IN/OUT command.
At the end of execution, ASCMP interrupt occurs. The bit setting is also valid in FIFO-DMA mode.
*AUTO: During execution of AUTO1 or 2, the AUTO bit of the SCSIMODE1 register is assumed to be "1".
The EXEC bit also becomes "1" during execution of AUTO1 or 2. Since the internal sequencer writes the
command into the SCSI block in place of the CPU, the COMMAND register can read the command value in
process of execution at that time.
BIT1 ACTIVE NEGATION CONTROL
When this bit is HIGH it enables the active negation function of the SCSI XSREQ/XSACK signals.
BIT0 ACTIVE NEGATION DATA
When this bit is HIGH it enables the active negation function of the SCSI data and parity signals.
32
Bit Symbol
7: -
6: -
5: -
4: ULTRA
3: AUTO1
2: AUTO2
1: AN_C
0: AN_D
EPSON
Description
ULTRA SCSI
AUTO1 (auto status)
AUTO2 (status message stop)
ACTIVE NEGATION CONTROL
ACTIVE NEGATION DATA
It is valid only when the RATE bit of the
Rev.1.0
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