Scsi Interrupt Status 2 (Scsiint2) R/W - Epson S1R72105 Technical Manual

7.3.30 SCSI Interrupt Status 2 (SCSIINT2) R/W

Shows the result of executing the SCSI control command.
The CPU identifies the source of interruption by reading this register after receiving the interrupt signal. It
clears the bit by writing the value read again.
Address Register Name
22h SCSIINT2
BIT7 RESERVED
BIT6 SCSI RST ASSERTION DETECTED
This bit becomes HIGH when SCSI RST is asserted.
BIT5 OFFSET ERROR IN SYNCHRONOUS TRANSFER
This bit becomes HIGH when an offset error occurs during synchronous transfer. The offset error means that the
offset counter is not reset to "0" when transfer ends or that the counter overflows/underflows.
BIT4 UNDEFIND GROUP COMMAND
This bit becomes HIGH when SCSI command other than group 0, 1, 2, or 5 is received.
BIT3 COMMAND ERROR
This bit becomes HIGH when other control command is issued during execution of the command, although an
undefined SCSI control command is issued.
BIT2 RESELECTED
This bit becomes HIGH when a re-selection is made from other device during execution of a command other than the
SCSI control command that makes a re-selection.
BIT1 SELECTED
This bit becomes HIGH when selected from other device during execution of a command other than SCSI control
command that makes a selection.
BIT0 LOST ARBITRATION
This bit becomes HIGH when defeated in the arbitration phase. When this bit is HIGH and it is not selected or
re-selected by other device, the IC suspends operation of the control commands.
Rev.1.0
Bit Symbol
7: -
6: SRST
5: OFERR
4: UNDEF
3: CMDER
2: RESEL
1: SEL
0: LARBT
EPSON
S1R72105 Technical Manual
Description
SCSI RST ASSERTION DETECTED
OFFSET ERROR IN SYNCHRONOUS TRANSFER
UNDEFIND GROUP COMMAND
COMMAND ERROR
RESELECTED
SELECTETD
LOST ARBITRATION
31