Ep{R}(R=A,B,C) Control(Eprcontrol) R/W - Epson S1R72105 Technical Manual

S1R72105 Technical Manual
7.5.2.10 EP {r}(r=a,b,c) Control (EPrControl) R/W
Sets operation for transaction in the direction of the endpoint set in the EPrConfig_0 register.
USBIndex : 01h to 03h
Address Register Name
1Ah EPrControl
BIT7 Force NAK
Setting this bit to HIGH returns NAK to transaction.
When there is a transaction that is being executed, setting of this bit a fixed period of time after starting transaction
becomes valid from the next transaction.
BIT6 Force STALL
Setting this bit to HIGH returns STALL to transaction.
Setting this bit to HIGH gives a STALL response to transaction.
When there is a transaction that is being executed, setting of this bit a fixed period of time after starting transaction
becomes valid from the next transaction.
BIT5 Short Packet (IN Transaction Only)
Setting this bit to HIGH returns packet to IN Transaction independent of amount of data of FIFO.
When packet transfer is completed after setting this bit to HIGH this bit returns to LOW.
BIT3 Toggle Mode (IN Transaction Only)
Sets the Toggle Mode.
0: Normal Mode
1: Fake Mode
BIT2 Toggle Status
Shows the Toggle Sequence bit during transaction.
Updated when transfer is completed by returning Short Packet for IN Transaction or when ACK is received from the
host for OUT Transaction.
BIT1 Toggle Clear
Sets the Toggle Sequence bit during transaction to 0.
BIT0 Toggle Set
Sets the Toggle Sequence bit during transaction to 1.
48
Bit Symbol
7: ForceNAK
6: ForceSTALL
5: EnShortPkt
4: 0
3: ToggleMode
2: ToggleStat
1: ToggleClr
0: ToggleSet
EPSON
Description
Force NAK
Force STALL
Short Packet (IN Transaction Only)
Reserved
Toggle Mode (IN Transaction Only)
Toggle Status
Toggle Clear
Toggle Set
Rev.1.0