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S1R72104 Technical Manual
7.3.10 SCSI Own ID (OWNID) R/W
Sets the SCSI-ID of this IC itself.
7
6
5
-
-
-
7.3.11 Source/Destination ID (SDID) R/W
Sets both the SCSI-ID of the selector side and the target SCSI-ID when selection is made.
7
6
5
-
SID2
SID1
In Initiator mode, sets the target SCSI-ID to be selected in DESTINATION ID.
When re-selection is received, the target SCSI-ID which made re-selection is set in SOURCE ID.
In Target mode, sets the initiator SCSI-ID to be re-selected in DESTINATION ID.
When selection is received, the initiator SCSI-ID which made selection is set in SOURCE ID.
7.3.12 Selection Timeout Counter (SLTIME) R/W
Sets time-out delay for selection and re-selection.
7
6
5
ST7
ST6
ST5
The time-out delay value is calculated according to the following formula:
Delay value = count value × 2
Where, T is internal clock cycle (40MHz).
The IC acts as follows if it detected time-out:
Suspends to output ID bit.
Negates XSSEL 4000×T×2 (about 200µs) after such suspension, and outputs selection time-out interrupt.
No time-out is detected if "0" is set to this register.
7.3.13 FIFO Control (FIFOCTL) R/W
Used for clearing the data of SCSI-FIFO and for checking its status.
7
6
5
-
-
-
BIT7,6,5,4,3 RESERVED
BIT2 CLEAR FIFO
HIGH of this bit clears the data stored in SCSI-FIFO.
The bit returns to LOW automatically after such clearing.
BIT1 FULL
HIGH of this bit means that SCSI-FIFO is full. In such a condition, any data written in SCSI-FIFO is ignored.
BIT0 EMPTY
HIGH of this bit means that SCSI-FIFO is empty. In such a condition, any trial to read data from SCSI-FIFO results
in invalid data read out.
16
4
3
2
-
-
OID2
4
3
2
SID0
-
DID2
4
3
2
ST4
ST3
ST2
×T×2
15
4
3
2
-
-
FCLR
1
0
0Eh
OID2
OID0
1
0
0Fh
DID1
DID0
DESTINATION ID (R)
SOURCE ID (R/W)
1
0
10h
ST1
ST0
1
0
11h
FULL
EMPTY
FIFO EMPTY
FIFO FULL
CLEAR FIFO
EPSON
Rev.1.1
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