Dma Write (Pslv=0: Master Mode) - Epson S1R72105 Technical Manual

8.4.3.3 DMA Write (PSLV=0: Master mode)

PDREQ(I)
XPDACK(0)
XPWR(0)
PD15-0(0)
Symbol
T
333
T
334
T
335
T
336
T
337
T
338
T
339
T
33A
Note 1: Data is output to PD only while both XPDACK and XPWR are asserted.
PD is always in Input mode except such time.
Rev.1.0
Direction of data transfer
T
334
T
338
Specification
XPWR ↓ → PDREQ negate
PDREQ negate delay time
XPDACK ↓ → XPWR ↓
XPWR setup time
XPWR ↓ → XPWR ↑
XPWR assert pulse width
XPWR ↑ → XPWR ↓
XPWR negate pulse width
XPWR ↑ → XPDACK ↑
XPWR hold time
XPWR ↓ → PD
Data output delay time Note 1
XPWR ↑ → PD(Hi-Z)
Data bus negate time Note 1
PDREQ negate → XPDACK ↑
XPDACK setup time
Prosessor
T T
335 336
T
339
Min.
0
0
- (AP+2)×25
- (NP+2)×25
0
0
5
5
EPSON
S1R72105 Technical Manual
S1R72105
T T
333 33A
T
337
Typ. Max.
- 30
- 5
-
-
- 5
- 25
- 40
- -
HOST
Unit
ns
ns
ns
ns
ns
ns
ns
ns
83