Epson S1R72105 Technical Manual page 59

Assert_ATN (07H)
Asserts the SCSI ATN signal (XSATN).
The command is valid only in Initiator mode. If issued in Target mode, it is ignored.
Also, it is not asserted in the busfree condition, however, no error occurs.
It causes no interruption after its execution.
Any other command being executed continues execution.
Negation of ATN occurs in any of the following cases:
When the last byte is ACK-negated after the Message_Out command is issued.
When busfree is detected.
When the Assert_RST command is executed.
When chip-reset is done.
SEL_MSG_clear (08H)
Negates the SCSI SEL/MSG signal (XSSEL/XSMSG).
When SCAM is selectted by Wait_SCAM_Selection_Command, the SCAM protocol is processed in Direct
mode, with SEL/MSG asserted left inside. This command is used to clear it. After issuing this command,
release Direct mode.
It causes no interruption after its execution.
Any other command being executed continues execution.
Select_WithoutATN (09H)
Executes selection without asserting the SCSI ATN signal.
This command is valid in both disconnected and connected conditions. Issuing this command while any other
command in execution causes a command error.
After the command is issued, operation of the IC is as follows:
Waits until the SCSI bus becomes busfree.
Enters arbitration after detecting busfree.
If it beats arbitration, it asserts XSSEL and ID bit to data bus, going into the selection phase.
It terminates selection and operation when its counterpart asserts XSBSY.
After completion, it sets the GOOD bit of the MAININT register.
It causes an interruption.
After that, the IC goes into Initiator mode.
Select_WithATN_Command (0AH)
Asserts SCSI ATN signal, executes selection, and then executes the message-out command phase.
This command is valid in both disconnected and connected condition. Issuing this command while any other
command is in execution causes a command error.
The CPU sets the message byte number in the NON-DMA data-size register before issuing this command.
Then, the CPU write message data in FIFO. After transferring the message, it sets the number of byte of
command in the NON-DMA data-size register and writes the command data into FIFO.
The IC operates as follows:
Waits for busfree.
After detecting busfree, enters arbitration.
When it beats arbitration, it asserts XSSEL and ID bit and then goes into the selection phase.
Asserts XSATN at this time.
After selection, it checks message-out at the timing when XSREQ is asserted and transfers messages in FIFO.
Negates XSATN after asserting XSREQ and before asserting XSACK at the last byte of the messages.
After transferring all the messages, it checks the command phase, detects data accumulated in FIFO, and
transfers the command data in FIFO according to the byte number newly set.
After completion, it sets the GOOD bit of the MAININT register.
It causes an interruption.
After that, the IC goes into Initiator mode.
Note: Be sure to write data into FIFO after setting the number of bytes of transfer.
Rev.1.0
S1R72105 Technical Manual
EPSON 53