Epson S1R72105 Technical Manual page 61

Wait_Reselect(0EH)
Waits for the re-selection phase.
Valid only when it is not connected.
Issuing this command in the connected condition sets the SCSIINT2 and CMDER bits and causes an
interruption. Any other command being executed continues execution.
The IC operates as follows:
Enters a state of waiting for re-selection.
After completion, it sets the GOOD bit of the MAININT register.
It causes an interruption.
After that, the IC goes into Initiator mode.
Wait_SCAM_Selection_Command (0FH)
Waits for SCAM selection and causes an interruption after the selection is made.
Valid only when it is not connected.
Issuing this command in the connected condition sets the SCSIINT2 and CMDER bits and causes an
interruption. Any other command being executed continues execution.
When issuing this command, set STATN (bit5) of the SCSIMODE register and clear it when the command is
terminated.
After issuing the command, the IC operates as follows:
Waits for the SCAM/normal selection phase.
Does not respond to, but ignores the SCSI selection with the selection time-out delay less than 4ms.
Responds to the SCAM selection and causes an interruption.
If no SCAM selection occurs, the IC responds to the selection which continues for 4ms or longer and after that
it operates as in the case of Wait_Select_Command (0Ch).
After that, the IC goes into Target mode.
Negate_ACK (11H)
Clears ACK left asserted by the last message transfer in Initiator mode when the LSI stops operation.
Command_Out (12H)
Executes the SCSI command phase.
Valid only in the connected condition. It can be issued in either Target or Initiator mode.
Issuing this command in the disconnected condition sets the SCSIINT2 and CMDER bits and causes an
interruption.
In Target mode
The IC operates as follows:
Enters this command into FIFO after setting the number of bytes of command in the NON-DMA data-size
register.
This control command does not distinguish command groups automatically. It is used for receiving a group
command which has undefined command block length.
After completion, it sets the GOOD bit of the MAININT register.
It causes an interruption.
The CPU reads a command from FIFO.
In Initiator mode
The CPU issues this command after setting the number of bytes of the command in the NON-DMA data-size
register.
Then it writes the command data into FIFO.
The IC operates as follows:
At the start of execution, negates XSACK if it is asserted.
Transfers the command data in FIFO after checking the command phase at the timing of assertion of XSREQ.
When FIFO is empty, places the REQ-ACK handshake on hold until data is accumulate in FIFO.
After completion, it sets the GOOD bit of the MAININT register.
It causes an interruption.
Rev.1.0
S1R72105 Technical Manual
EPSON 55