Scsi Control (Scsictl) R/W; Scsi Data (Scsidata) R/W - Epson S1R72105 Technical Manual

S1R72105 Technical Manual

7.3.33 SCSI Control (SCSICTL) R/W

This register is accessed when the CPU directly controls SCSI signal lines.
For such direct control, DIRECT (bit 1) must be set in the mode setting register (0Ah).
The status of each signal is stored as "active high".
Address Register Name
2Bh SCSICTL

7.3.34 SCSI Data (SCSIDATA) R/W

This register is accessed when the CPU directly controls the SCSI data bus. For such direct control, DIRECT
(bit 1) must be set in the mode setting register (0Ah).
The status of each signal is stored as "active high". The DIRECT setting does not determine whether the
parity bit is output or not. It is output if it has been output before setting DIRECT, or it is not otherwise.
Address Register Name
2Ch SCSIDATA
34
Bit Symbol
7: ACK
6: ATN
5: SEL
4: BSY
3: REQ
2: MSG
1: I/O
0: C/D
Bit Symbol
7: DB7
6: DB6
5: DB5
4: DB4
3: DB3
2: DB2
1: DB1
0: DB0
EPSON
Description
SCSI ACK
SCSI ATN
SCSI SEL
SCSI BSY
SCSI REQ
SCSI MSG
SCSI I/O
SCSI C/D
Description
SCSIDATA
Rev.1.0