ZiLOG Z8 Series User Manual
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ZiLOG Z8 Series User Manual

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Z8 Family of Microcontrollers
®
Z8
CPU
User Manual
UM001604-0108
®
Copyright ©2008 by Zilog
, Inc. All rights reserved.
www.zilog.com

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Summary of Contents for ZiLOG Z8 Series

  • Page 1 Z8 Family of Microcontrollers ® User Manual UM001604-0108 ® Copyright ©2008 by Zilog , Inc. All rights reserved. www.zilog.com...
  • Page 2 TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this document has been verified according to the general principles of electrical and mechanical engineering. Z8 is the registered trademark of Zilog, Inc. All other product or service names are the property of their respective owners.
  • Page 3 For more details, refer to the corresponding pages and appropriate links in the table below. Date Revision Description Page No Level January Updated Zilog logo, Zilog text, Disclaimer section, 2008 and implemented Style Guide. February Changed the OP code to B0 and B1 in Instruction 2007 Description.

  • Page 4: Table Of Contents

    ® User Manual Table of Contents ® CPU Product Overview ..........1 Key Features .
  • Page 5 ® User Manual Input/Output Ports ..........43 Mode Registers .
  • Page 6 ® User Manual Prescaler Operations ..........84 Modes .
  • Page 7 ® User Manual Serial Peripheral Interface ......... . 122 SPI Operation .

  • Page 8: Z8 ® Cpu Product Overview

    Zilog’s Z8 microcontroller (MCU) product line continues to expand with new product introductions. Zilog MCU products are targeted for cost-sensitive, high-volume applica- tions including consumer, automotive, security, and HVAC. It includes ROM-based prod- ucts geared for high-volume production (where software is stable) and one-time...
  • Page 9 ® User Manual default WDT clock source is an internal RC circuit (isolated from the device clock source). All family devices have internal Power-On Reset. Auto Reset/Low-Voltage Protection— ROM devices add low-voltage protection. Low-voltage protection ensures the MCU is in a known state at all times (in active RUN or RESET modes) without external hardware (or a device reset pin).

  • Page 10: Product Development Support

    Note: Z86Cxx signify ROM devices; 86xx signify EPROM devices; F = fixed; P = programmable. The Z86CCP01ZEM kit includes: • Z8 CCP evaluation board • Z8 CCP power cable • Zilog Developer Studio (ZDS) CD-ROM, Including Windows-Based GUI Host Soft- ware • 1999 Zilog Technical Library • Z8 CCP User Manual ®...
  • Page 11 ® User Manual A Z8 CCP Emulator Accessory Kit (Z8CCP00ZAC) is also available and provides an RS- 232 cable and power cable along with the 28- and 40- pin ZIF sockets and 28- and 40-pin target connector cables required to emulate/program 28-/40-pin devices. ®...

  • Page 12: Address Space

    ® User Manual Address Space Introduction ® CPU includes the following four address spaces: • The Z8 Standard Register File contains addresses for peripheral, control, all general- purpose, and all I/O port registers. This is the default register file specification. •...
  • Page 13 ® User Manual Table 2. Z8 Standard Register File (Continued) Register Hex Address Identifier Register Description Timer/Counter 0 PRE1 T1 Prescaler Timer/Counter 1 Timer Mode Serial I/O R239 General-Purpose Registers (GPR) Port 3 Port 2 Port 1 Port 0 Registers can be accessed as either 8-bit or 16-bit registers using Direct, Indirect, or Indexed Addressing.

  • Page 14: General-Purpose Registers

    ® User Manual MASK AND R15, DFh ;Clear Bit 5 of Working Register 15 Figure 3. Accessing Individual Bits (Example) When instructions are executed, registers are read when defined as sources and written when defined as destinations. All General-Purpose Registers function as accumulators, address pointers, index registers, stack areas, or scratch pad memory.
  • Page 15 ® User Manual With 4-bit addressing, the register file is logically divided into 16 Working Register Groups of 16 registers each, as listed in Table 3. These 16 registers are known as Working Registers. A Register Pointer (one of the control registers, ) contains the base address of the active Working Register Group.
  • Page 16 ® User Manual Register Pointer (FDh), Standard Register File INC R6 (instruction, short format) Actual register address (76h) Figure 4. Working Register Addressing Examples R253 R7 R6 R5 R4 R3 R2 R1 R0 (Register Pointer) The upper nibble of the register file address, provided by the register pointer, specifies the active working-register group.

  • Page 17: Error Conditions

    ® User Manual Error Conditions ® Registers in the Z8 Standard Register File must be correctly used because certain condi- tions produce inconsistent results and should be avoided. • Registers – are write-only registers. If an attempt is made to read these registers, is returned.
  • Page 18 ® User Manual Expanded Register File Bank (F) (F) 0F WDTMR (F) 0E (F) 0E Reserved Reserved (F) 0D Reserved Register Pointer (F) 0C Reserved D7 D6 D5 D4 D3 D2 D1 D0 (F) 0B Working Register Expanded Register Group Pointer (F) 0A Reserved Group Pointer...
  • Page 19 ® User Manual When an ERF Bank is selected, register addresses access those sixteen ERF ® Bank registers—in effect replacing the first sixteen locations of the Z8 Standard Register File. For example, if ERF Bank C is selected, the Z8 Standard Registers through no longer accessible.
  • Page 20 ® User Manual Table 4. ERF Bank Address (Continued) Register Pointer Hex Register File (FDh) Low Nibble 1001b Expanded Register File Bank 9 1010b Expanded Register File Bank A 1011b Expanded Register File Bank B 1100b Expanded Register File Bank C 1101b Expanded Register File Bank D 1110b...
  • Page 21 ® User Manual Table 5. Register Pointer Access Example (Continued) If R253 RP = FFh ;ERF Bank F, Working Reg. Group F. 00h = PCON R0 = SI0 01h = Reserved R1 = TMR 02h = Reserved R2 = T1 0Bh = SMR R15 = SPL 0Fh = WDTMR...

  • Page 22: Z8 ® Control And Peripheral Registers

    ® User Manual Table 7. Z8 ERF Bank Layout ERF Bank ERF PCON, SMR, WDT, (00h, 0Bh, 0Fh), Working Register Group 0 only implemented. Not implemented (reserved) Not implemented (reserved) SPI Registers: SCOMP, RXBUF, SCON (00h, 01h, 02h), Working Register Group 0 only implemented. Not implemented (reserved) Not implemented (reserved) Not implemented (reserved)

  • Page 23: Expanded Z8 Registers

    ® User Manual • Program Control Flags (FLAGS) • Register Pointer (RP) • Stack Pointer High-Byte (SPH) • Stack Pointer Low-Byte (SPL) ® The Z8 CPU uses a 16-bit Program Counter (PC) to determine the sequence of current program instructions. The PC is not an addressable register. Peripheral registers are used to transfer data, configure the operating mode, and control the operation of the on-chip peripherals.
  • Page 24 ® User Manual Table 8. ERF Bank C WR Group 0 (Continued) Register Function Working Register Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SPI Control (SCON) SPI Tx/Rx Data (Roxburgh) SPI Compare (SCOMP) ® Working Register Group 0 in ERF Bank 0 consists of the registers for Z8 General-Pur- pose Registers and ports.
  • Page 25 ® User Manual Table 9. ERF Bank 0 WR Group 0 (Continued) Register Function Working Register General-Purpose Register Port 3 Port 2 Port 1 Port 0 Working Register Group 0 in ERF Bank F consists of the control registers for STOP mode, WDT, and port control.

  • Page 26: Program Memory

    ® User Manual Program Memory The first 12 bytes of Program Memory are reserved for the interrupt vectors, as displayed Figure 8 on page 20. These locations contain six 16-bit vectors that correspond to the six available interrupts. Address 12 up to the maximum ROM address consists of on-chip mask-programmable ROM.

  • Page 27: Z8 ® External Memory

    ® User Manual 65535 External ROM and RAM 4096 4095 Location of On–Chip First Byte of Instruction Executed After RESET Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte) ® Figure 8. Z8 Program Memory Map ® External Memory Z8 CPU, in some cases, has the capability to access external Program Memory with the 16-bit Program Counter.

  • Page 28: External Data Memory

    ® User Manual External Data Memory The Z8 CPU, in some cases, can address up to 60 KB of external data memory beginning at location 4096. External data memory (DM) can be included with, or separated from, the external Program Memory space. DM, an optional I/O function that can be programmed to appear on pin P34, is used to distinguish between data and Program Memory space.

  • Page 29: Z8 ® Stacks

    ® User Manual ® Stacks Stack operations can occur in either the Z8 Standard Register File or external data mem- ory. Under software control, Port 0–1 Mode register ( ) selects the stack location. Only the General-Purpose Registers can be used for the stack when the internal stack is selected.
  • Page 30 ® User Manual Top of Stack Top of Stack FLAGS Stack Contents Stack Contents After a Call After an Instruction Interrupt Cycle Figure 11. Stack Operations UM001604-0108 Address Space...

  • Page 31: Clock

    ® User Manual Clock ® CPU derives its timing from on-board clock circuitry connected to pins XTAL1 and XTAL2. The clock circuitry consists of an oscillator, a divide-by-two shaping circuit, and a clock buffer. Figure 12 displays the clock circuitry. The oscillator’s input is XTAL1 and its output is XTAL2.

  • Page 32: Sclk ÷ Tclk Divide-By-16 Select

    ® User Manual SMR (F) OB D7 D6 D5 D4 D3 D2 D1 D0 SCLK ÷ TCLK Divide by 16 0 OFF ** 1 ON External Clock Divide Mode by 2 0 = SCLK ÷ TCLK = XTAL ÷ 2* 1 = SCLK ÷...

  • Page 33: Oscillator Control

    ® User Manual D1 (SMR) ÷ D0 (SMR) ÷ External Clock Figure 14. External Clock Circuit Oscillator Control ® In some cases, the Z8 CPU offers software control of the oscillator to select low EMI drive or standard drive. The selection is done by programming bit D7 of the Port Configu- ration (PCON) register (see Figure 15 on page 26).

  • Page 34: Oscillator Operation

    ® For fast and reliable oscillator start-up over the manufacturing process range, Zilog rec- ommends that the load capacitors be sized as low as possible without resulting in overtone operation.

  • Page 35: Layout

    ® User Manual Layout ® Traces connecting crystal, caps, and the Z8 CPU oscillator pins should be as short and wide as possible. This reduces parasitic inductance and resistance. The components (caps, crystal, resistors) should be placed as close as possible to the oscillator pins of the Z8 CPU.

  • Page 36: Crystals And Resonators

    ® User Manual Signal Line Layout Should XTAL1 20 mm Avoid High Lighted Areas Z8 CPU XTAL2 Clock Generator Circuit Signals A B ® (Parallel Traces Must Be Avoided) Signal C Board Design Example (Top View) Z8 CPU (Connection to System Group Must Be Avoided) Figure 17.
  • Page 37 ® User Manual Depending on operation frequency, the oscillator may require the addition of capacitors C1 and C2 (displayed in Figure 18). The capacitance values are dependent on the manu- facturer’s crystal specifications. ® XTAL1 XTAL2 Figure 18. Crystal/Ceramic Resonator Oscillator XTAL1 ®...

  • Page 38: Lc Oscillator

    V is not on XTAL1. Zilog recommends that in applications where the Z8 CPU is exposed to much system noise, a diode from XTAL1 to V be used to prevent acciden- tal enabling of these modes.

  • Page 39: Rc Oscillator

    ® User Manual Simple series capacitance is calculated using the following equation: If C = 2C Sample calculation for capacitance C and C of 5.83 MHz frequency and inductance value of 27 µH. 5.83 (10 –6 2π [2.7 (10 ] 1/2 = 27.6 pF Therefore, C = 55.2 pF and C...

  • Page 40: Reset

    ® User Manual Reset ® This section describes the Z8 CPU reset conditions, reset timing, and register initializa- tion procedures. Reset is generated by Power-On Reset (POR), Reset Pin, Watchdog Timer (WDT), and Stop Mode Recovery. A system reset overrides all other operating conditions and puts the Z8 CPU into a known state.
  • Page 41 ® User Manual Table 12. Sample Control and Peripheral Register Reset Values (ERF Bank 0) Bits Register (Hex) Register Name Comments Serial I/O Timer Mode 0 Counter/Timers stopped. Counter/Timer1 T1 Prescaler 0 Single-pass count mode, external clock source. Counter/Timer0 T0 Prescaler 0 Single-pass count mode.
  • Page 42 ® User Manual First Machine Cycle Clock SCLK Hold Low For 4 SCLK RESET Periods (Minimum) First Instruction Fetch Figure 22. Reset Timing After a reset, the first routine executed should be one that initializes the control registers to the required system configuration. ®...
  • Page 43 ® User Manual 100 KΩ RESET 200 KΩ 1 µF 10 V Figure 23. Example of External Power-On Reset Circuit Table 13. ERF Bank 0 Reset Values at RESET Bits Register (Hex) Register Name Comments Port 0 U Input mode, output set to push–pull. Port 1 U Input mode, output set to push–pull.
  • Page 44 ® User Manual Table 15. Sample Expanded Register File Bank F Reset Values Bits Register (Hex) Register Name Comments Port Configuration 0 Comparator outputs disabled on Port 3. (PCON) Port 0 and 1 output is push–pull. Port 0, 1, 2, 3, and oscillator with standard output drive.
  • Page 45 ® User Manual RESET 4 Clock Clear 18 Clock RESET RESET Filter Generator Internal RESET WDT Select WDT TAP SELECT (WDTMR) CLK Source Select (WDTMR) XTAL 256 TpC 1024 4096 WDT/POR Counter Chain OSC. 2.6 V Operating Voltage Det. 2.6V REF From Stop Mode Recovery Source Stop Delay...
  • Page 46 ® User Manual CLEAR 18 Clock RESET RESET 4 Clock Filter Generator Internal RESET WDT Select WDT TAP SELECT (WDTMR) CLK Source Select (WDTMR) XTAL 5ms POR 5 ms 15 ms 25 ms 100 ms WDT/POR Counter Chain Internal RC OSC. 2 V Operating Voltage Det.

  • Page 47: Watchdog Timer

    ® User Manual Watchdog Timer ® The WDT is a retriggerable one-shot timer that resets the Z8 CPU if it reaches its termi- nal count. When operating in the RUN or HALT modes, a WDT reset is functionally equivalent to a hardware POR reset. The WDT is initially enabled by executing the WDT instruction and refreshed on subsequent executions of the WDT instruction.
  • Page 48 ® User Manual The WDTMR register is accessible only during the first 60 processor cycles from the exe- cution of the first instruction after Power-On Reset, Watchdog Reset, or a Stop Mode Recovery. After this point, the register cannot be modified by any means, intentional or otherwise.

  • Page 49: Power-On Reset

    ® User Manual Bits 5, 6, and 7—These bits are reserved. Voltage Comparator—An on-board voltage comparator checks that V is at the required level to insure correct operation of the device. Reset is globally driven if V below the specified voltage. This feature is available in select ROM Z8 devices. See the device product specification for feature availability and operating range.

  • Page 50: Input/Output Ports

    ® User Manual Input/Output Ports ® CPU features up to 32 lines dedicated to input and output. These lines are grouped into four 8-bit ports known as Port 0, Port 1, Port 2, and Port 3. Port 0 is nibble program- mable as input, output, or address.

  • Page 51: Input And Output Registers

    ® User Manual Input and Output Registers Each bit of Ports 0, 1, and 2, has an input register, an output register, associated buffer, and control logic. Because there are separate input and output registers associated with each port, writing to bits defined as inputs stores the data in the output register. This data cannot be read as long as the bits are defined as inputs.

  • Page 52: General I/O Mode

    ® User Manual Port I/O Lines Input Input Buffer Register Read Port Internal Timing Handshake DAV/RDY Selected Handshake Handshake Logic Logic Write Port RDY/DAV Output Output Buffer Register Output Enable Internal Figure 29. Ports 0, 1, 2 Generic Block Diagram General I/O Mode Port 0 can be an 8-bit, bidirectional, CMOS or TTL compatible I/O port.
  • Page 53 ® User Manual Port 1 (I/O or AD15–AD08) Handshake Controls DAV0 and RDY0 (P32 and P35) OPEN-DRAIN 2.3 V Hysteresis Autolatch R ≈ 500 KΩ Figure 30. Port 0 Configuration with Open-Drain Capability, Autolatch, and Schmitt-Trigger UM001604-0108 Input/Output Ports...

  • Page 54: Read/Write Operations

    ® User Manual TTL Level Shifter Figure 31. Port 0 Configuration with TTL Level Shifter Read/Write Operations In the nibble I/O Mode, Port 0 is accessed as general-purpose register P0 ( ) with ERF Bank set to 0. The port is written by specifying P0 as an instruction's destination register. Writing to the port causes data to be stored in the port's output register.

  • Page 55: Port 1

    ® User Manual DAV0 (P32) and RDY0 (P35) when Port 0 is an input port, or RDY0 (P32) and DAV0 (P35) when Port 0 is an output port (see Figure 33 on page 49). Handshake direction is determined by the configuration (input or output) assigned to the Port 0 upper nibble:P04–P07.
  • Page 56 ® User Manual Register F7h Port 3 Mode Register (P3M) (Write-Only) 0 P32 = Input P35 = Output 1 P32 = DAV0/RDY0 P35 = RDY0/DAV0 Figure 33. Port 0 Handshake Operation Port 1 (I/O or AD7–AD0) Handshake Controls DAV1 and RDY1 (P33 and P34) OPEN-DRAIN 2.3 V Hysteresis...

  • Page 57: Read/Write Operations

    ® User Manual Port 1 (I/O or AD7–AD0) Handshake Controls DAV1 and RDY1 (P33 and P34) TTL Level Shifter Figure 35. Port 1 Configuration with TTL Level Shifter Read/Write Operations In byte input or byte output mode, the port is accessed as General-Purpose Register P1 ).

  • Page 58: Handshake Operations

    ® User Manual Using the Port 0–1 Mode Register, Port 1 is configured as an output port by setting bits D4 and D3 to 0, or as an input port by setting D4 to 0 and D3 to 1 (see Figure 36).

  • Page 59: Port 2

    ® User Manual Port 2 Port 2 is a general-purpose port. Figure 29 on page 45 displays a block diagram of Port 2. Each of its lines can be independently programmed as input or output via the Port 2 Mode Register ( ) as seen in Figure...
  • Page 60 ® User Manual OPEN-DRAIN P21–P26 OE P21–P26 P21–P26 OUT 2.3 V Hysteresis @ V = 5.0 V P21–P26 IN Autolatch R ≈ 500 KΩ Figure 39. Port 2 Configuration with Open-Drain Capability, Autolatch, and Schmitt-Trigger Open-Drain TTL Level Shifter Figure 40. Port 2 Configuration with TTL Level Shifter UM001604-0108 Input/Output Ports...

  • Page 61: Read/Write Operations

    ® User Manual OPEN-DRAIN P20 OE SPI EN P20 OUT P20 IN SPI DI Autolatch R ≈ 500 KΩ OPEN-DRAIN Standard P27 OUT SPI DO Standard P27 OE SPI Active SCON 0 SOI D0 Enable 1 P27 OUT *SPI must be enabled with D0 P27 IN Autolatch R ≈...

  • Page 62: Handshake Operation

    ® User Manual open-drain output, the data returned is the value forced on the output pin by the external system. This may not be the same as the data in the output register. Reading input bits of Port 2 also returns data on the external pins. However, inputs under handshake control return data latched into the input register via the input strobe.

  • Page 63: Port 3

    ® User Manual Port 3 General Port I/O Port 3 differs structurally from Ports 0, 1, and 2. Port 3 lines are fixed as four inputs (P33– P30) and four outputs (P37–P34) Port 3 does not have an input and output register for each bit.
  • Page 64 ® User Manual Read Port Port Input Input Input Input Buffer Buffer Lines Register –P3 To Interrupt Timer, Handshake Logic, or Serial I/O Read Port Output Data Return Buffer Write Port Port Output Output Output Output Output Output Buffer Register Register Buffer Register...
  • Page 65 ® User Manual Port 3 (I/O or Control) Autolatch R ≈ 500 KΩ P30 Data Latch IRQ3 R247 = P3M 1 = Analog 0 = Digital DIG. P31 (AN1) IRQ2, T , P31 Data Latch P32 (AN2) IRQ0, P32 Data Latch P33 (REF) From Stop-Mode IRQ1, P33 Data Latch...
  • Page 66 ® User Manual P37 OUT REF (P33) P37 OUT REF (P33) PCON 0 P34, P37 Standard Output 1 P34, P37 Comparator Output Figure 46. Port 3 Configuration with Comparator UM001604-0108 Input/Output Ports...
  • Page 67 ® User Manual SK IN SPI EN SPI MSTR SPI EN SK OUT P34 OUT SPI EN SPI MSTR P34 OUT PCON 0 P34, P35 Standard Output 1 P34, P35 Comparator Output Figure 47. Port 3 Configuration with SPI and Comparator Outputs UM001604-0108 Input/Output Ports...

  • Page 68: Read/Write Operations

    ® User Manual Port 3 Output Configuration TTL Level Shifter Port 3 Input Configuration Autolatch R ≈ 500 KΩ Figure 48. Port 3 Configuration with TTL Level Shifter and Autolatch Read/Write Operations Port 3 is accessed as a General-Purpose Register P3 ( ).
  • Page 69 ® User Manual Register F7h Port 3 Mode Register (Write-Only) D7 D6 D5 D4 D3 D2 D1 D0 0 Port 2 Open-Drain 1 Port 2 Push–Pull 0 P31, P32 Digital Mode 1 P31, P32 Analog Mode 0 P32 = Input P35 = Output 00 P33 = Input P34 = Output...

  • Page 70: Port Handshake

    ® User Manual Table 17. Port 3 Line Functions (Continued) Function Line Signal Port 0 Handshake Output RDY0/DAV0 Port 1 Handshake Output RDY1/DAV1 Port 2 Handshake Output RDY2/DAV2 Analog Comparator Input Analog Comparator Output AN1-OUT AN2-OUT AN2-OUT Interrupt Requests IRQ3 IRQ2 IRQ0 IRQ1...
  • Page 71 ® User Manual the port is not protected and can be overwritten by the Z8 CPU during the handshake sequence. To avoid losing data, the software must not overwrite the port until the corre- sponding interrupt request indicates that the external device has latched the data. The software can always read Port 3 output and input handshake lines, but cannot write to the output handshake line.
  • Page 72 ® User Manual (Input To Z8) (Output From Z8) Data on Port (Output From Z8) Valid Data State 1. RDY input is High indicating that the I/O device is ready to accept data. ® the Z8 CPU Writes to the port register to initiate a data transfer. Writing to the port outputs new data and State 2.

  • Page 73: I/O Port Reset Conditions

    ® User Manual P20–P27 Device Figure 52. Output Strobed Handshake on Port 2 P20–P27 Device Figure 53. Input Strobed Handshake on Port 2 I/O Port Reset Conditions Full Reset After a hardware reset, WDT reset, or a POR, Port Mode Registers P01M, P2M, and P3M are set as displayed in Figure 54 on page 67 through...
  • Page 74 ® User Manual ® Because the types and amounts of I/O vary greatly among the Z8 CPU family devices, it is Note: recommended to review the selected device's product specifications for the register default state after reset. Register F8h Port 0–1 Mode Register (P01M) (Write-Only) P00–P03 Mode 00 = Output...

  • Page 75: Analog Comparators

    ® User Manual Register F7h Port 3 Mode Register (P3M) (Write-Only) 0 Port 2 Open-Drain 1 Port 2 Push–Pull 0 P31, P32 Digital Mode 1 P31, P32 Analog Mode 0 P32 = Input P35 = Output 1 P32 = DAV0/RDY0 P35 = RDY0/DAV0 00 P33 = Input P34 = Output...
  • Page 76 ® User Manual Port 3 inputs must be in digital mode if Port 3 is a Stop Mode Recovery source. The analog comparator is disabled in STOP mode. P31 can be used as T in analog or digital modes, but it must be referenced to P33, when in analog mode.
  • Page 77 ® User Manual Port 3 (I/O or Control) Autolatch R ≈ 500 KΩ P30 Data Latch IRQ3 R247 = P3M 1 = Analog 0 = Digital DIG. P31 (AN1) IRQ2, T , P31 Data Latch P32 (AN2) IRQ0, P32 Data Latch P33 (REF) From Stop-Mode IRQ1, P33 Data Latch...

  • Page 78: Comparator Programming

    ® User Manual P34 OUT REF (P33) P37 OUT REF (P33) PCON 0 P34, P37 Standard Output 1 P34, P37 Comparator Output Figure 60. Port 3 Configuration Comparator Programming Example of enabling analog comparator mode. LD P3M, #XXXX XX1Xb = any binary number Example of enabling analog comparator output.

  • Page 79: Comparator Operation

    ® User Manual LD R0, #XXXX XXX1b ;Enables comparator ;outputs using PCON ;Register programming Comparator Operation After enabling the Analog Comparator mode, P33 becomes a common reference input for both comparators. The P33 (Ref) is hard wired to the reference inputs to both comparators and cannot be separated.

  • Page 80: Run Mode

    ® User Manual For CMOS voltage comparator inputs, the input offset current (I ) is the leakage current of the CMOS input gate. Run Mode P33 is not available as an interrupt input during analog mode. P31 and P32 are valid inter- rupt inputs in conjunction with P33 (Ref) when in analog mode.

  • Page 81: Low Emi Emission

    ® User Manual Other Z8 MCUs feature a Port Configuration Register (PCON) for which Port 0 and Port 1 can be configured to provide open-drain outputs. The PCON Register is located in ERF Bank F, Register . See Figure 62 on page 74.

  • Page 82: Input Protection

    ® User Manual • Low EMI output drivers have resistance of 200 Ω (typical) • Low EMI Oscillator • All output drivers are approximately 25 percent of the standard drive • Internal SCLK ÷ TCLK = XTAL operation limited to a maximum of 4 MHz–250 ns cycle time, when Low EMI Oscillator is selected and system clock (SCLK = XTAL, SMR Reg.
  • Page 83 ® User Manual Figure 63. Diode Input Protection ® On CMOS OTP EPROM Z8 MCUs, the Port 3 inputs P31, P32, P33, and the XTAL 1 pin have only the input protection diode from pad to V . See Figure Figure 64.

  • Page 84: Z8 ® Cmos Autolatches

    ® User Manual ® CMOS Autolatches I/O port bits that are configurable as inputs are protected against open circuit conditions using autolatches. An autolatch is a circuit which, in the event of an open circuit condition, latches the input at a valid CMOS level. This inhibits the tendency of the input transistors to self-bias in the forward active region, thus drawing excessive supply current.

  • Page 85: Autolatch Model

    ® User Manual second occurs when the input is connected to the output of a device with tri-state capabil- ity. The autolatch also activates when the input voltage at the pin is not within 200 microvolts or so of either supply rail. In this case, the circuit draws current, which is not significant compared to the I operating current of the device, but increases I STOP mode cur-...
  • Page 86 ® User Manual Vil (max), pullup or pull-down resistances must be calculated using Ref = R/Rp. For best case STOP mode operation, the inputs should be within 200 mV of the supply rails. In output mode, if a port bit is forced into a tri-state condition, the autolatches force the pad to V .

  • Page 87: Counters And Timers

    ® User Manual Counters and Timers ® CPU provides up to two 8-bit counter/timers, T0 and T1, each driven by its own 6-bit prescaler, PRE0 and PRE1 (see Figure 68). Both counter/timers are independent of the processor instruction sequence, that relieves software from time-critical operations such as interval timing or event counting.

  • Page 88: Prescalers And Counter/Timers

    ® User Manual ) using P31. Port 3 line P36 can serve as a timer output (T ) through which T0, T1, or the internal clock can be output. The timer output toggles at the end-of-count. The counter/timer, prescaler, and associated mode registers are mapped into the register file as displayed in Figure 69.
  • Page 89 ® User Manual R245 PRE0 Prescaler 0 Register (%F5; Write-Only) D7 D6 D5 D4 D3 D2 D1 D0 Count Mode 0 = T Single Pass 1 = T Modulo-n Reserved (Must be 0) Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX) Figure 70.

  • Page 90: Counter/Timer Operation

    ® User Manual R242 T1 Counter/Timer 1 Register (%F2; Write/Read Only) R244 T0 Counter/Timer 0 Register (%F4; Write/Read Only) D7 D6 D5 D4 D3 D2 D1 D0 Initial value when written (Range 1-256 decimal, 01-00 HEX) current value when read Figure 72.

  • Page 91: Prescaler Operations

    ® User Manual The counter timers remain at rest as long as the Enable Count bits are 0. To enable count- ing, the Enable Count bit (D for T0 and D for T1) must be set to 1. Counting actually starts when the Enable Count bit is written by an instruction.
  • Page 92 ® User Manual 82). When the Prescaler Counter reaches its end-of-count, the initial value is reloaded and counting continues. The prescaler never actually reaches 0. For example, if the prescaler is set to divide-by-three, the count sequence is: 3–2–1–3–2–1–3–2–1–3... Each time the prescaler reaches its end of count a carry is generated, that allows the Counter/Timer to decrement by one on the next timer clock input.

  • Page 93: Tout Modes

    ® User Manual Minimum duration is achieved by loading (1 prescaler output count), maximum dura- tion is achieved by loading (256 prescaler outputs counts). The prescaler and counter/timer are true divide-by-n counters. Modes The Timer Mode Register TMR ( ; see Figure 76), is used in conjunction with the Port 3 Mode Register P3M (...
  • Page 94 ® User Manual and bit 6 to 1 and 0, respectively. The counter/timer T mode is turned off by setting TMR bit and bit 6 both to 0, freeing P36 to be a data output line. is initialized to a logic 1 whenever the TMR Load bit (bit 0 for T0 or bit 1 for T2) is set to 1.

  • Page 95: Tin Modes

    ® User Manual Internal Clock ÷ TMR D TMR D Figure 79. Internal Clock Output Through T Modes The Timer Mode Register TMR ( ; see Figure 80 on page 89) is used in conjunction with the Prescaler Register PRE1 ( ;...

  • Page 96: External Clock Input Mode

    ® User Manual Register F1h Timer Mode Register (TMR) (Read/Write) D5 D4 = Modes: External Clock Input = 00 Gate Input = 01 Trigger Input = 10 (Non-retriggerable) Trigger Input = 11 (Retriggerable) Figure 80. Timer Mode Register (T Operation) Register F3h Prescaler 1 Register (PRE1) (Write-Only)

  • Page 97: Gated Internal Clock Mode

    ® User Manual –D = 00 PRE1 Clock Internal Clock Figure 82. External Clock Input Mode Gated Internal Clock Mode The T Gated Internal Clock Mode (TMR bit 5 and bit 4 set to 0 and 1 respectively) mea- sures the duration of an external event. In this mode, the T1 prescaler is driven by the internal timer clock, gated by a High level on T (see Figure...

  • Page 98: Retriggerable Input Mode

    ® User Manual T1 is triggered counting continues until software resets the Enable Count bit. Interrupt request IRQ5 is generated when T1 reaches its end-of-count. ÷ Internal Clock ÷ PRE1 Edge Trigger Trigger –D Figure 84. Triggered Clock Mode Retriggerable Input Mode The T Retriggerable Input Mode (TMR bits 5 and 4 are set to 1) causes T1 to load and start counting on every occurrence of a High-to-Low transition on T...

  • Page 99: Reset Conditions

    ® User Manual ÷ ÷ ÷ PRE1 PRE0 Figure 85. Cascaded Counter/Timers Reset Conditions After a hardware reset, the counter/timers are disabled and the contents of the counter/ timer and prescaler registers are undefined. However, the counting modes are configured for Single-Pass and the T1 clock source is set for external.
  • Page 100 ® User Manual R243 PRE1 RESCALER EGISTER (%F3; W RITE OUNT 0 = T INGLE 1 = T ODULO LOCK OURCE 1 = T NTERNAL 0 = T XTERNAL RESCALER ODULO : 1–64 D ANGE ECIMAL 01–00 HEX) Figure 87. Prescaler 1 Register Reset R245 PRE0 Prescaler 0 Register (%F5;...
  • Page 101 ® User Manual R241 TMR Timer Mode Register (% F1; Read/Write) 0 = No Function 1 = Load T 0 = Disable T Count 1 = Enable T Count 0 = No Function 1 = Load T 0 = Disable T Count 1 = Enable T Count...

  • Page 102: Interrupts

    ® User Manual Interrupts ® CPU allows 6 different interrupts from a variety of sources; up to four external inputs, the on-chip Counter/Timer(s), software, and serial I/O peripherals. These interrupts can be masked and their priorities are set by using the Interrupt Mask and the Interrupt Priority Registers.

  • Page 103: Interrupt Sources

    ® User Manual –IRQ Global Interrupt Enable Interrupt Request Priority Logic Vector Select Figure 91. Interrupt Block Diagram Note: See the selected Z8 CPU's product specification for the exact interrupt sources supported. Interrupt Sources Table 18 on page 97 describes the interrupt types, sources, and vectors available in the ®...

  • Page 104: External Interrupt Sources

    ® User Manual Table 18. Interrupt Types, Sources, and Vectors Name Sources Vector Location Comments DAV0, IRQ0, Comparator External (P32), Edge Triggered; Internal DAV1, IRQ1 External (P33), Edge Triggered; Internal DAV2, IRQ2, T , Comparator External (P31), Edge Triggered; Internal IRQ3 External (P30) or (P32), Edge Triggered;...

  • Page 105: Internal Interrupt Sources

    ® User Manual IRQ3 can be generated from an external source only if Serial In is not enabled. Otherwise, its source is internal. The external request is generated by a Low edge signal on P30 as dis- played in Figure 93.

  • Page 106: Interrupt Initialization

    ® User Manual At sample time the request is transferred to the second flip-flop in Figure 94, that drives the interrupt mask and priority logic. When an interrupt cycle occurs, this flip-flop is reset only for the highest priority level that is enabled. You have direct access to the second flip-flop by reading and writing the IRQ Register.

  • Page 107: Interrupt Priority Register Initialization

    ® User Manual Interrupt Priority Register Initialization The Interrupt Priority Register (IPR) displayed in Figure 96 is a write-only register that sets priorities for the vectored interrupts in order to resolve simultaneous interrupt requests. (There are 48 sequence possibilities for interrupts.) The six interrupt levels IRQ0-IRQ5 are divided into three groups of two interrupt requests each.

  • Page 108: Interrupt Mask Register Initialization

    ® User Manual Table 19. Interrupt Priority (Continued) Priority Group Value Highest Lowest Bit 2 IRQ2 IRQ0 IRQ0 IRQ2 Bit 5 IRQ5 IRQ3 IRQ3 IRQ5 Table 20. Interrupt Group Priority Bit Pattern Group Priority Bit 4 Bit 3 Bit 0 High Medium Not Used...

  • Page 109: Interrupt Request Register Initialization

    ® User Manual Register FBh Interrupt Request Register (IMR) (Read/Write) D7 D6 D5 D4 D3 D2 D1 D0 0 = Disables IRQ0 1 = Enables IRQ0 0 = Disables IRQ1 1 = Enables IRQ1 0 = Disables IRQ2 1 = Enables IRQ2 0 = Disables IRQ3 1 = Enables IRQ3 0 = Disables IRQ4...
  • Page 110 ® User Manual // Enable IRQ register, otherwise read only. // Not required if interrupts were previously enabled. // Disable interrupt heading. Note: IRQ is always cleared to and is read only until the first EI instruction, which enables the IRQ to be read/written. Register FAh Interrupt Request Register (IRQ) (Read/Write)

  • Page 111: Irq Software Interrupt Generation

    ® User Manual Table 21. IRQ Register Configuration* Interrupt Edge * F = Falling Edge; R = Rising Edge. The proper sequence for programming the interrupt edge select bits is (assumes IPR and IMR have been previously initialized). ;Inhibit all interrupts until input edges are configured.

  • Page 112: Vectored Processing

    ® User Manual To generate a SWI, the appropriate request bit in the IRQ is set as follows: ORIRQ, #NUMBER where the immediate data, NUMBER, has a 1 in the bit position corresponding to the appropriate level of the SWI. For example, if an SWI is required on IRQ5, NUMBER would have a 1 in bit 5: OR IRQ, #00100000b With this instruction, if the interrupt system is globally enabled, IRQ5 is enabled, and...
  • Page 113 ® User Manual SP and Stack before an interrupt SP and Stack after an interrupt Top of Stack PC LOW Byte PC HIGH Byte FLAGS Figure 100. Effects of an Interrupt on the Stack UM001604-0108 Interrupts...

  • Page 114: Vectored Interrupt Cycle Timing

    ® User Manual Program Memory XXFFh Interrupt Service Routine PC HIGH Byte FLAGS 000Ch Vector Selected By Priority Logic Interrupt Vector Table 0000h Figure 101. Interrupt Vectoring Vectored Interrupt Cycle Timing The interrupt acknowledge cycle time is 24 internal clock cycles and is displayed in Figure 102 on page 108.

  • Page 115: Nesting Of Vectored Interrupts

    ® User Manual longest instruction present in the application program + 2T C (internal synchronization time). Fetch Fetch Stack Push Stack Push Stack Push Vector High Vector Low Internal Clock For Stack External Only Odd Vector Address A0-A7 OUT PC+1 SP-1 SP-2 SP-3 FLAGS...

  • Page 116: Reset Conditions

    ® User Manual EI ;Enable interrupt mechanism DI ;Disable vectored interrupts. To initiate polled processing, check the bits of interest in the IRQ using the Test Under Mask (TM) instruction. If the bit is set, call or branch to the service routine. The service routine services the request, resets its Request Bit in the IRQ, and branches or returns back to the main program.

  • Page 117: Power-Down Modes

    ® User Manual Power-Down Modes ® In addition to the standard RUN mode, the Z8 CPU supports two Power-Down modes to minimize device current consumption. The two modes supported are HALT and STOP. Halt Mode Operation HALT mode suspends instruction execution and turns off the internal CPU clock. The on- chip oscillator circuit remains active so the internal clock continues to run and is applied to the Counter/Timer(s) and interrupt logic.
  • Page 118 ® User Manual NOP instruction (opcode = ) immediately before the STOP instruction (opcode = ), that is, FF NOP ;clear the instruction pipeline 6F STOP ;enter STOP mode STOP mode is exited by any one of the following resets: POR activation, WDT time out (if available), or a Stop Mode Recovery source.

  • Page 119: Stop Mode Recovery Register

    ® User Manual Stop Mode Recovery Register This register selects the clock divide value and determines the mode of Stop Mode Recov- ery (see Figure 103). All bits are Write-Only, except bit 7, that is Read-Only. Bit 7 is a flag bit that is hardware set on the condition of stop-recovery and reset by a power-on cycle.
  • Page 120 ® User Manual external clock frequency when this bit is set (D1 = 1). Using this bit together with D7 of PCON helps further lower EMI (D7 (PCON) = 0, D1 (SMR) = 1). The default setting is zero. Stop Mode Recovery Source—The D2, D3, and D4 bits of the SMR specify the wake-up source of the stop-recovery and (Table 22 Figure 104...
  • Page 121 ® User Manual SMR D4 D3 D2 SMR D4 D3 D2 SMR D4 D3 D2 SMR D4 D3 D2 SMR D4 D3 D2 SMR D4 D3 D2 To POR RESET Stop Mode Recovery Edge Select (SMR) To P33 Data Latch and IRQ P33 From Pads Digital/Analog Mode Select (P3M)

  • Page 122: Serial Input/Output

    ® User Manual Serial Input/Output UART Introduction ® Some Z8 CPU microcontrollers contain an on-board full-duplex Universal Asynchro- nous Receiver/Transmitter (UART) for data communications. The UART consists of a serial input/output (SIO) Register located at address , and its associated control logic (see Figure 105).

  • Page 123: Uart Bit-Rate Generation

    ® User Manual Table 23. UART Register Map Register Name Identifier Hex Address Port 3 Mode T0 Prescaler PRE0 Timer/Counter0 Timer Mode UART UART Bit-Rate Generation When Port 3 Mode Register bit 6 is set to 1, the UART is enabled and T0 automatically becomes the bit rate generator (see Figure 106).
  • Page 124 ® User Manual ® To configure Z8 CPU for a specific bit rate, appropriate values as determined by the above equation must be loaded into registers PRE0 ) and T0 ( ). PRE0 also controls the counting mode for T0 and should therefore be set to CONTINUOUS mode (D0 = 1).

  • Page 125: Uart Receiver Operation

    ® User Manual The bit rate generator is started by setting the Timer Mode Register (TMR) ( ) bit 1 and bit 0 both to 1 (see Figure 109). This transfers the contents of the Prescaler 0 Register and Counter/Timer0 Register to their corresponding down counters. In addition, counting is enabled so that UART operations begin.

  • Page 126: Overwrites

    ® User Manual Stop Bit One or More Start Bit Transition Detected RCVR Data Shift Clock Eight T0 Counts Later Shifting Starts RCVR IRQ3 Shift register Contents Transferred to Receive Buffer and IRQ3 is Generated Figure 110. Receiver Timing After a full character has been assembled in the receiver’s buffer, SIO Register ( Interrupt Request IRQ3 is generated.

  • Page 127: Transmitter Operation

    ® User Manual Received Data SP D7 D6 D5 D4 D3 D2 D1 D0 ST (No Parity) Start Bit Eight Data Bits One Stop Bit Received Data SP P D6 D5 D4 D3 D2 D1 D0 ST (With Parity) Start Bit Seven Data Bits Parity Error Flag One Stop Bit...

  • Page 128: Overwrites

    ® User Manual T0’s output drives a divide-by-16 counter that in turn generates a shift clock every 16 counts. This counter is reset when the transmitter buffer is written by an instruction. This reset synchronizes the shift clock to the software. The transmitter then outputs one bit per shift clock, through Port 3 bit 7, until a start bit, the character written to the buffer, and two stop bits have been transmitted.

  • Page 129: Uart Reset Conditions

    ® User Manual UART Reset Conditions After a hardware reset, the SIO Register contents are undefined, and Serial Mode and par- ity are disabled. Figure 114 Figure 115 display the binary reset values of the SIO Reg- ister and its associated mode register P3M. Register RF0h Serial I/O Register (SIO) (Read/Write)
  • Page 130 ® User Manual Mode Recovery, Master/Slave selection, and Compare mode. Table 25 contains the pin configuration for the SPI feature when it is enabled. The SPI consists of four registers: SPI Control Register (SCON), SPI Compare Register (SCOMP), SPI Receive/Buffer Register (RxBUF), and SPI Shift Register.
  • Page 131 ® User Manual SCON (C) 02 D7 D6 D5 D4 D3 D2 D1 D0 SPI Enable 0 Disable * 1 Enable RxCharOverrun (S) 0 Reset 1 Overrun CLK Divide (M) 00 TCLK/2 01 TCLK/4 10 TCLK/8 11 TCLK/16 DO SPI Port Enable (S) 0 SPI DO Port Enable 1 Do Port to I/O Compare Enable...

  • Page 132: Spi Operation

    ® User Manual SPI Operation The SPI is used in one of two modes: either as system slave, or as system master. Several of the possible system configurations are displayed in Figure 117 on page 126. In slave mode, data transfer starts when the slave select (SS) pin goes active. Data is transferred into the slave’s SPI Shift Register through the DI pin, which has the same address as the RxBUF Register.

  • Page 133: Receive Character Available And Overrun

    ® User Manual sion of the internal system clock if this is used as the SPI clock source. Divide by 2, 4, 8, or 16 is chosen as the scaler. Standard Serial Setup Master ss sk do di ss sk do di ss sk do di ss sk do di Slave...
  • Page 134 ® User Manual slave modes. While in slave mode, if the RxBUF is not read before the next data stream is received and loaded into the RxBUF Register, Receive Character Overrun (RxCharOver- run) occurs. Because there is no requirement for clock control in slave mode, bit D1 in the SPI Control Register is used to log any RxCharOverrun (see Figure 118 Figure 119...
  • Page 135 ® User Manual Port Control SPI Compare Register (SCOMP) Bit Control /Interrupt Control SPI Shift Register SPI Receive Buffer (RxBUF) SPI Control Clock SCLK + n TCLK Figure 119. SPI Logic UM001604-0108 Serial Input/Output...
  • Page 136 ® User Manual OPEN-DRAIN P20 OE SPI EN P20 IN SPI DI Autolatch R ≈ 500 KΩ OPEN-DRAIN Standard P27 OUT SPI DO SPI DO Standard P27 OE SPI Active SCON 0 SOI D0 Enable 1 P27 OUT *SPI must be enabled with D0 P27 IN Autolatch R ≈...
  • Page 137 ® User Manual SK IN SPI EN SPI MSTR SPI EN SK OUT P34 OUT SPI EN SPI MSTR P35 OUT PCON 0 P34, P35 Standard Output 1 P34, P35 Comparator Output Figure 121. SPI Clock/SPI Slave Select Output Configuration UM001604-0108 Serial Input/Output...

  • Page 138: External Interface

    ® User Manual External Interface Introduction ® CPU can be a microcontroller with 20 pins for external memory interfacing. The external memory interface on the Z8 CPU is generally for either RAM or ROM; this fea- tures is only available for devices featuring Port 0, Port 1, R/W, DM, AS, and DS. Refer to specific product specifications for availability of these features.

  • Page 139: External Addressing Configuration

    ® User Manual Data Strobe (Output, Active Low)—Data Strobe (DS) provides the timing for data movement to or from the Address/Data bus for each external memory transfer. During a Write Cycle, data out is valid at the leading edge of the DS. During a Read Cycle, data in must be valid prior to the trailing edge of the DS.

  • Page 140: External Stacks

    ® User Manual Port 0 can be programmed to provide either four additional address lines (A11–A8), which increases the addressable memory to 4 KB, or eight additional address lines (A15–A8), which increases the addressable external memory up to 64 KB. It is required to add a NOP after configuring Port 0/Port 1 for external addressing before jumping to external memory execution.

  • Page 141: Data Memory

    ® User Manual Register F8h (P01M) Port 0–1 Register (Write-Only) D7 D6 D5 D4 D3 D2 D1 D0 Z8 Stack Selection 0 = External 1 = Internal ® Figure 124. Z8 Stack Selection Data Memory The two Z8 external memory spaces, data and program, are addressed as two separate spaces of up to 64 KB each.
  • Page 142 ® User Manual clock is shown for clarity only and does not have a specific timing relationship with other signals. Machine Cycle Clock A15-A8 A8-A15 AD7–AD0 A7–A0 D7–D0 IN Read Cycle *Port inputs are strobed during T2, which is two internal systems clocks before the execution cycle of the current instruction.

  • Page 143: Address Strobe

    ® User Manual Machine Cycle Clock A15-A8 A8-A15 D7–D0 OUT AD7–AD0 A7–A0 Write Cycle Figure 127. External Memory Write Cycle Address Strobe ® All transactions start with AS driven Low and then raised High by Z8 CPU. The rising edge of AS indicates that R/W, DM (if used), and the address outputs are valid. The address outputs (AD7–AD0), remain valid only during MnT1 and typically must be latched using AS.

  • Page 144: Extended Bus Timing

    ® User Manual Extended Bus Timing Some products can accommodate slow memory access time by automatically inserting an additional software controlled state time (Tx). This stretches the DS timing by two clock periods. Figure 128 Figure 129 on page 138 display extended external memory Read and Write cycles.

  • Page 145: Instruction Timing

    ® User Manual Machine Cycle Clock A15-A8 A15–A8 AD7–AD0 A7–A0 D7–D0 OUT Write Cycle Figure 129. Extended External Memory Write Cycle Timing is extended by setting bit D5 in the Port 0–1 Mode Register ( ) to 1 (see Figure 130).
  • Page 146 ® User Manual the current instruction, the opcode of the next instruction is fetched. Instruction pipelining is displayed in Figure 131. Figure 131 Figure 132 on page 139 display typical instruction cycle timing for instructions fetched from memory. For those instructions that require execution time longer than that of the overlapped fetch, or reference program or data memory as part of their execution, the pipe must be flushed.Figure 131...

  • Page 147: Z8 ® Reset Conditions

    ® User Manual ® Reset Conditions After a hardware reset, extended timing is set to accommodate slow memory access dur- ing the configuration routine, DM is inactive, the stack resides in the register file. Port 0, 1, and 2 are reset to input mode. Port 2 is set to Open-Drain Mode. UM001604-0108 External Interface...

  • Page 148: Instruction Set

    ® User Manual Instruction Set ® instructions can be divided functionally into the following eight groups: • Load • Bit Manipulation • Arithmetic • Block Transfer • Logical • Rotate and Shift • Program Control • CPU Control The following summary shows the instructions belonging to each group and the number of operands required for each.
  • Page 149 ® User Manual Table 27. Arithmetic Instructions (Continued) Mnemonic Operands Instruction Increment Increment Word INCW Subtract with Carry dst, src Subtract dst, src Table 28. Logical Instructions Mnemonic Operands Instruction Logical AND dst, src Complement Logical OR dst, src Logical Exclusive OR dst, src Table 29.
  • Page 150 ® User Manual Table 31. Block Transfer Instructions Mnemonic Operands Instruction Load Constant Auto Increment LDCI dst, src Load External Auto Increment LDEI dst, src Table 32. Rotate and Shift Instructions Mnemonic Operands Instruction Rotate Left Rotate Left Through Carry Rotate Right Rotate Right Through Carry Shift Right Arithmetic...

  • Page 151: Processor Flags

    ® User Manual Processor Flags ® The Flag Register informs about the current status of Z8 CPU. The flags and their (FCh) bit positions in the Flag Register are displayed in Figure 133. Z8 Flag Register contains six bits of status information which are set or cleared by CPU operations.

  • Page 152: Zero Flag

    ® User Manual Zero Flag For arithmetic and logical operations, the Zero Flag (Z) is set to 1 if the result is zero. Oth- erwise, the Zero Flag is cleared to 0. If the result of testing bits in a register is , the Zero Flag is set to 1.

  • Page 153: Half Carry Flag

    ® User Manual IRET changes the value of the Decimal Adjust Flag when the Flag Register saved in the Stack is restored. Half Carry Flag The Half Carry Flag (H) is set to 1 whenever an addition generates a carry bit 3 (Over- flow) or a subtraction generates a borrow bit 3.

  • Page 154: Notation And Binary Encoding

    ® User Manual Table 36. Condition Codes Binary Mnemonic Definition Flag Settings 0000 Always False — 1000 (blank) Always True — 0111 Carry C = 1 1111 No Carry C = 0 0110 Zero Z = 1 1110 Non-Zero Z = 0 1101 Plus S = 0...
  • Page 155 ® User Manual Table 37. Notational Shorthand Notation Address Mode Operand Range * Condition Code Condition Codes Working Register n = 0–15 Register Reg. represents a number in the range of 00h to Working Register n = 0–15 Register Pair Reg.

  • Page 156: Assembly Language Syntax

    ® User Manual Additional symbols used are listed in Table Table 38. Additional Symbols Symbol Definition Destination Operand Source Operand Indirect Address Prefix Stack Pointer Program Counter FLAGS Flag Register (FCh) Register Pointer (FDh) Interrupt Mask Register (FBh) Immediate Operand Prefix Hexadecimal Number Prefix Hexadecimal Number Suffix Binary Number Suffix...

  • Page 157: Z8 ® Instruction Summary

    ® User Manual ASM: 43h, (ADD dst, src) OBJ: (OPC src, dst) In general, whenever an instruction format requires an 8-bit register address, that address can specify any register location in the range 0–255 or a Working Register R0–R15. If, in the above example, register is a Working Register, the assembly syntax and resulting object code would be:...
  • Page 158 ® User Manual Table 39. Summary of Z8 Instruction Set (Continued) Address Mode Flags Affected Op Code Instruction and Operation Byte (Hex) CP dst, src † A[ ] – – dst − src DA dst – – dst ← DA dst DEC dst –...
  • Page 159 ® User Manual Table 39. Summary of Z8 Instruction Set (Continued) Address Mode Flags Affected Op Code Instruction and Operation Byte (Hex) JP cc, dst – – – – – – if cc is true, c = 0–F then PC ← dst JR cc, dst –...
  • Page 160 ® User Manual Table 39. Summary of Z8 Instruction Set (Continued) Address Mode Flags Affected Op Code Instruction and Operation Byte (Hex) dst ← src and r ← r + 1 or rr ←rr + 1 – – – – –...
  • Page 161 ® User Manual Table 39. Summary of Z8 Instruction Set (Continued) Address Mode Flags Affected Op Code Instruction and Operation Byte (Hex) SRP dst – – – – – – RP ← src STOP – – – – – – SUB dst, src †...
  • Page 162 ® User Manual Table 40 provides a summary of Z8 address modes. ® Table 40. Summary of Z8 Address Modes Address Mode Lower Op Code Nibble UM001604-0108 Instruction Set...

  • Page 163: Op Code Map

    ® User Manual Op Code Map Figure 134 displays the opcode map. Lower Nibble (Hex) 10.5 10.5 10.5 10.5 12/10.5 12/10.0 12.10.0 DJNZ r1, r2 r1, Ir2 R2, R1 IR2, R1 R1, IM IR1, IM r1, R2 r2, R1 r1, RA cc, RA r1, IM cc, DA...

  • Page 164: Instruction Description

    ® User Manual Instruction Description Table 41 provides quick reference to each of the ZTP process manipulation functions. Table 41. Process Manipulation Functions Logical OR Add With Carry Logical Exclusive OR Call Procedure Complement Carry Flag PUSH Clear Reset Carry Flag Complement Return Compare...
  • Page 165 ® User Manual Syntax ADD dst, src Instruction Format Address Mode Cycles OPC (Hex) Operation dst ← dst + src The source operand is added to the destination operand. Two’s complement addition is performed. The sum is stored in the destination operand. The contents of the source oper- and are not affected.
  • Page 166 ® User Manual Example 1 If Working Register R3 contains and Working Register R11 contains , the state- ment: ADD R3, R11 Op Code: 02 3B leaves the value in Working Register R3. The C, Z, S, V, D, and H Flags are all cleared.
  • Page 167 ® User Manual Example 6 If Register contains and Register contains , the statement: ADD @D4h, #02h Op Code: 07 D4 02 leaves the value in Register . The C, Z, S, V, D, and H Flags are all cleared. UM001604-0108 Instruction Description...
  • Page 168 ® User Manual Add With Carry Syntax ADC dst, src Instruction Format Address Mode Cycles (Hex) Operation dst ← dst + src + C The source operand, along with the setting of the Carry (C) Flag, is added to the destina- tion operand.
  • Page 169 ® User Manual Example 1 If Working Register R3 contains , the C Flag is set to 1, and Working Register R11 contains , the statement: ADC R3, R11 Op Code: 12 3B leaves the value in Working Register R3. The C, Z, S, V, D, and H Flags are all cleared.
  • Page 170 ® User Manual Example 6 If Register contains , Register contains , and the C Flag is set, the state- ment: ADC @D4h, #02h Op Code: 17 D4 02 leaves the value in Register . The C, Z, S, V, D, and H Flags are all cleared. UM001604-0108 Instruction Description...
  • Page 171 ® User Manual Call Procedure Syntax CALL dst Instruction Format Address Mode Cycles (Hex) Operation SP ← SP–2 @SP ← PC PC ← dst The Stack pointer is decremented by two, the current contents of the Program Counter (PC) (address of the first instruction following the CALL instruction) are pushed onto the top of the Stack, and the specified destination address is then loaded into the PC.
  • Page 172 ® User Manual Example 1 If the contents of the PC are 1A47h and the contents of the SP (Registers ) are 3002h, the statement: CALL 3521h Op Code: D6 35 21 causes the SP to be decremented to (the address following the CALL 3000h 1A4Ah instruction) to be stored in external data memory 3000 and 3001h, and the PC to be loaded...
  • Page 173 ® User Manual Complement Carry Flag Syntax Instruction Format Cycles (Hex) Operation C ← NOT C The C Flag is complemented. If C = 1, then it is changed to C = 0; or, if C = 0, then it is changed to C = 1.
  • Page 174 ® User Manual Clear Syntax CLR dst Instruction Format Address Cycles (Hex) Operation dst ← 0 The destination operand is cleared to Flag Description Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected Note: Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the destination Working Register operand is specified by adding ) to the high nibble 1110b...
  • Page 175 ® User Manual Complement Syntax COM dst Instruction Format Address Mode Cycles (Hex) Operation dst ← NOT dst The contents of the destination operand are complemented (one’s complement). All 1 bits are changed to 0, and all 0 bits are changed to 1. Flag Description Unaffected...
  • Page 176 ® User Manual Example 2 If Register contains , and Register contains ), the state- 11111111b ment: COM @08h Op Code: 61 08 leaves the value ) in Register . The Z Flag is set, and the V and S 00000000b Flags are cleared.
  • Page 177 ® User Manual Compare Syntax CP dst, src Instruction Format Address Mode Cycles (Hex) Operation dst–src The source operand is compared to (subtracted from) the destination operand, and the appropriate Flags are set accordingly. The contents of both operands are unaffected. Flag Description Cleared if there is a carry from the most significant bit of the result.
  • Page 178 ® User Manual If Working Register R3 contains and Working Register R11 contains , the state- ment: CP R3, R11 Op Code: A2 3B sets the C and S Flags, and the Z and V Flags are cleared. Example 2 If Working Register R15 contains , Working Register R10 contains , and Register...
  • Page 179 ® User Manual Decimal Adjust Syntax DA dst Instruction Format Address Mode Cycles (Hex) Operation dst ← DA dst The destination operand is adjusted to form two 4-bit BCD digits following a binary addi- tion or subtraction operation on BCD encoded bytes. For addition (ADD and ADC) or subtraction (SUB and SBC), the following table indicates the operation performed.
  • Page 180 ® User Manual Flag Description Set if there is a carry from the most significant bit; cleared otherwise (see table above). Set if the result is zero; cleared otherwise. Set if result bit 7 is set (negative); cleared otherwise. Unaffected Unaffected Note: Address modes R or IR can be used to specify a 4-bit Working Register.
  • Page 181 ® User Manual 0011 1100 = 3Ch Register contains the value , and the result of the addition is stored in Register , the statement: DA @45h Op Code: 40 45 adjusts this result so the correct BCD representation is obtained. 0011 1100 = 3Ch 0000 0110 = 06h 0100 0010 = 42h...
  • Page 182 ® User Manual Decrement Syntax DEC dst Instruction Format Address Cycles (Hex) Mode dst Operation dst ← dst–1 The contents of the destination operand are decremented by one. Flag Description Unaffected Set if the result is zero; cleared otherwise Set if the result of bit 7 is set (negative); cleared otherwise Set if arithmetic overflow occurs;...
  • Page 183 ® User Manual Decrement and Jump if Non-Zero Syntax DJNZ r, dst Instruction Format Address Mode Cycles OPC (Hex) 12 If jump taken 10 if jump not taken (R = 0 to F) Operation r ← r–1; If r <> 0, PC ← PC + dst The specified Working Register being used as a counter is decremented.
  • Page 184 ® User Manual • End the loop with DJNZ The assembly listing required for this routine is as follows: LD R6, 12 ;Load Counter LOOP: LD R9, @R6 ;Move one byte to LD @R6, R9 ;new location DJNZ R6, LOOP ;Decrement and Loop until counter ;= 0 UM001604-0108 Instruction Description...
  • Page 185 ® User Manual Decrement Word Syntax DECW dst Instruction Format Address Mode Cycles (Hex) Operation dst ← dst–1 The contents of the destination (which must be an even address) operand are decremented by one. The destination operand can be a Register Pair or a Working Register Pair. Flag Description Unaffected...
  • Page 186 ® User Manual DECW @R0 Op Code: 81 E0 leaves the value in Register Pair . The S Flag is set, and the Z and V FAF2h Flags are cleared. UM001604-0108 Instruction Description...
  • Page 187 ® User Manual Disable Interrupts Syntax Instruction Format Cycles (Hex) Operation IMR (7) ← 0 Bit 7 of Control Register (the Interrupt Mask Register) is reset to 0. All interrupts are disabled, although they remain potentially enabled. (For example, the Global Interrupt Enable is cleared, but not the individual interrupt level enables.) Flag Description...
  • Page 188 ® User Manual Enable Interrupts Syntax Instruction Format Cycles (Hex) Operation IMR (7) ← 0 Bit 7 of Control Register (the Interrupt Mask Register) is set to 1. This allows poten- tially enabled interrupts to become enabled. Flag Description Unaffected Unaffected Unaffected Unaffected...
  • Page 189 ® User Manual Halt Syntax HALT Instruction Format Cycles (Hex) Operation The HALT instruction turns off the internal CPU clock, but not the XTAL oscillation. The counter/timers and the external interrupts IRQ1, IRQ2, and IRQ3 remain active. The devices are recovered by interrupts, either externally or internally generated. Flag Description Unaffected...
  • Page 190 ® User Manual Increment Instruction Format Address Mode Cycles (Hex) Operation dst ← dst + 1 The contents of the destination operand are incremented by one. Flag Description Unaffected Set if the result is zero; cleared otherwise. Set if the result of bit 7 is set (negative); cleared otherwise. Set if arithmetic overflow occurs;...
  • Page 191 ® User Manual Example 3 If Register contains and Register contains , the statement: INC @B3h Op Code: 21 B3 leaves the value in Register . The Z Flag is set, and the V and S Flags are cleared. UM001604-0108 Instruction Description...
  • Page 192 ® User Manual Increment Word Syntax INCW dst Instruction Format Address Mode Cycles (Hex) Operation dst ← dst–1 The contents of the destination (which must be an even address) operand is decremented by one. The destination operand can be a Register Pair or a Working Register Pair. Flag Description Unaffected...
  • Page 193 ® User Manual Example 2 If Working Register R0 contains , and Register Pairs contain the value , the statement: FAF3h INCW @R0 Op Code: A1 E0 leaves the value in Register Pair . The S Flag is set, and the Z and V FAF4h Flags are cleared.
  • Page 194 ® User Manual Interrupt Return Syntax IRET Instruction Format Cycles (Hex) Operation FLAGS ← @SP SP ← SP + 1 PC ← @SP SP ← SP + 2 IMR (7) ← 1 This instruction is issued at the end of an interrupt service routine. It restores the Flag Reg- ister (Control Register ) and the PC.
  • Page 195 ® User Manual Jump Syntax JP cc, dst Instruction Format Address Mode Cycles OPC (Hex) 12 If jump taken cc OPC 10 If jump not taken cc = 0 to F Operation If cc (condition code) is true, then PC ← dst A conditional jump transfers Program Control to the destination address if the condition specified by cc (condition code) is true.
  • Page 196 ® User Manual replaces the contents of the Program Counter with 1520h and transfers program control to that location. If the Carry Flag had not been set, control would have fallen through to the statement following the JP instruction. Example 2 If Working Register Pair RR2 contains the value , the statement: 3F45h...
  • Page 197 ® User Manual Jump Relative Syntax JR cc, dst Instruction Format Address Mode Cycles OPC (Hex) 12 If jump taken cc OPC 10 if jump not taken cc = 0 to F Operation If cc is true, PC ← PC + dst If the condition specified by the cc is true, the relative address is added to the PC and con- trol passes to the instruction located at the address specified by the PC (see Condition...
  • Page 198 ® User Manual Load Syntax LD dst, src Instruction Format Address Mode Cycles (Hex) r = 0 to F Operation dst ← src The contents of the source operand are loaded into the destination operand. The contents of the source operand are not affected. Flag Description Unaffected...
  • Page 199 ® User Manual Address modes R or IR can be used to specify a 4-bit Working Register. In this format, the Note: source or destination Working Register operand is specified by adding ) to the 1110b high nibble of the operand. For example, if Working Register R12 (CH) is the destination operand, then is used as the destination operand in the Op Code.
  • Page 200 ® User Manual loads the value into Register . The contents of Working Register R12 and Work- ing Register R13 are not affected. Example 6 If Register contains the value , the statement: LD 34h, 45h Op Code: E4 45 34 loads the value into Register .
  • Page 201 ® User Manual Example 11 If Working Register R0 contains the value and Register ) con- tains the value , the statement: LD R10, 24h(R0) Op Code: C7 A0 24 loads Working Register R10 with the value . The contents of Working Register R0 and Register are not affected.
  • Page 202 ® User Manual Load Constant Syntax LDC dst, src Instruction Format Address Mode Cycles (Hex) Operation dst ← src This instruction is used to load a byte constant from Program Memory into a Working Register, or vice versa. The address of the Program Memory location is specified by a Working Register Pair.
  • Page 203 ® User Manual loads the value into Program Memory location . The value of Working Regis- 10A2h ter R2 is unchanged by the load. Note: This instruction format is valid only for MCUs which can address external program memory. UM001604-0108 Instruction Description...
  • Page 204 ® User Manual Load Constant Autoincrement Syntax LDCI dst, src Instruction Format Address Mode Cycles (Hex) Operation dst ← src r ← r + 1 rr ← rr + 1 This instruction is used for block transfers of data between Program Memory and the Reg- ister File.
  • Page 205 ® User Manual LDCI @R2, @RR6 Op Code: C3 26 loads the value into Register . Working Register Pair RR6 is incremented to and Working Register R2 is incremented to 30A4h Example 2 If Working Register R2 contains , Register contains , Register contains...
  • Page 206 ® User Manual Load External Data Syntax LDE dst, src Instruction Format Address Mode Cycles (Hex) Operation dst ← src This instruction is used to load a byte from external data memory into a Working Register or vice versa. The address of the external data memory location is specified by a Working Register Pair.
  • Page 207 ® User Manual loads the value into external data memory location 404Ah Note: This instruction format is valid only for MCUs which can address external data memory. UM001604-0108 Instruction Description...
  • Page 208 ® User Manual Load External Data Autoincrement Syntax LDEI dst, src Instruction Format Address Mode Cycles (Hex) Operation dst ← src r ← r + 1 rr ← rr + 1 This instruction is used for block transfers of data between external data memory and the Register File.
  • Page 209 ® User Manual LDEI @R2, @RR6 Op Code: 83 26 loads the value into Register . Working Register Pair RR6 is incremented to and Working Register R2 is incremented to 404Ch Example 2 If Working Register R2 contains , Register contains , Register contains...
  • Page 210 ® User Manual No Operation Syntax Instruction Format Cycles (Hex) Operation No action is performed by this instruction. It is typically used for timing delays or clearing the pipeline. Flag Description Unaffected Unaffected Unaffected Unaffected Unaffected Unaffected UM001604-0108 Instruction Description...
  • Page 211 ® User Manual Logical AND Syntax AND dst, src Instruction Format Address Mode Cycles (Hex) Operation dst ← dst AND src The source operand is logically ANDed with the destination operand. The AND operation results in a 1 being stored whenever the corresponding bits in the two operands are both 1, otherwise a 0 is stored.
  • Page 212 ® User Manual Example 1 If Working Register R1 contains ) and Working Register R14 contains 00111000b ), the statement: 10001101 AND R1, R14 Op Code: 52 1E Example 2 If Working Register R4 contains ), Working Register R13 contains 11111001b and Register contains...
  • Page 213 ® User Manual Example 6 If Working Register R3 contains the value and Register contains the value ), the statement: 11101100b AND @R3, #05h Op Code: 57 E3 05 leaves the value ) in Register . The Z, V, and S Flags are cleared. 00000100b UM001604-0108 Instruction Description...
  • Page 214 ® User Manual Logical OR Syntax OR dst, src Instruction Format Address Mode Cycles (Hex) Operation dst ← dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination operand. The contents of the source operand are not affected. The OR operation results in a one bit being stored whenever either of the corresponding bits in the two operands is a one.
  • Page 215 ® User Manual Example 1 If Working Register R1 contains ) and Working Register R14 contains 00111000b ), the statement: 10001101 OR R1, R14 Op Code: 42 1E leaves the value ) in Working Register R1. The S Flag is set, and the Z 10111101b and V Flags are cleared.
  • Page 216 ® User Manual Example 6 If Working Register R3 contains the value and Register contains the value ), the statement: 00001100b OR @R3, #05h Op Code: 57 E3 05 leaves the value ) in Register . The Z, V, and S Flags are cleared. 00001101b UM001604-0108 Instruction Description...
  • Page 217 ® User Manual Logical Exclusive OR Syntax XOR dst, src Instruction Format Address Mode Cycles (Hex) Operation dst ← dst XOR src The source operand is logically EXCLUSIVE ORed with the destination operand. The XOR operation results in a 1 being stored in the destination operand whenever the corre- sponding bits in the two operands are different, otherwise a 0 is stored.
  • Page 218 ® User Manual Example 1 If Working Register R1 contains ) and Working Register R14 contains 00111000b ), the statement: 10001101b XOR R1, R14 Op Code: B2 1E leaves the value ) in Working Register R1. The Z, and V Flags are 10111101b cleared, and the S Flag is set.
  • Page 219 ® User Manual Example 6 If Working Register R3 contains the value and Register contains the value ), the statement: 01101100b XOR @R3, #05h Op Code: B7 E3 05 leaves the value ) in Register . The Z, V, and S Flags are cleared. 01101001b UM001604-0108 Instruction Description...
  • Page 220 ® User Manual Syntax POP dst Instruction Format Address Mode Cycles (Hex) Operation dst ← @SP SP ← SP + 1 The contents of the location specified by the SP (Stack Pointer) are loaded into the desti- nation operand. The SP is then incremented automatically. Flag Description Unaffected...
  • Page 221 ® User Manual Example 2 If the SP (Control Registers ) contains the value , external data mem- 1000h ory location contains , and Working Register R6 contains , the statement: 1000h POP @R6 Op Code: 51 E6 loads the value into Register .
  • Page 222 ® User Manual PUSH Syntax PUSH src Instruction Format Address Mode Cycles (Hex) 10 Internal Stack 12 External Stack 10 Internal Stack 10 External Stack Operation SP ← SP–1 @SP ← src The contents of the SP (stack pointer) are decremented by one, then the contents of the source operand are loaded into the location addressed by the decremented SP, thus adding a new element to the stack.
  • Page 223 ® User Manual Example 2 If the SP contains and Working Register R4 contains , the statement: PUSH @R4 Op Code: 71 E4 stores the contents of Register (the Flag Register) in location . After the PUSH operation, the SP contains UM001604-0108 Instruction Description...
  • Page 224 ® User Manual Reset Carry Flag Syntax Instruction Format Cycles (Hex) Operation C ← 0 The C Flag is reset to 0, regardless of its previous value. Flag Description Reset to 0 Unaffected Unaffected Unaffected Unaffected Unaffected Example If the C Flag is currently set, the statement: Op Code: CF resets the Carry Flag to 0.
  • Page 225 ® User Manual Return Syntax Instruction Format Cycles (Hex) Operation PC ← @SP SP ← SP + 2 This instruction is normally used to return from a procedure entered by a CALL instruc- tion. The contents of the location addressed by the SP are popped into the PC. The next statement executed is the one addressed by the new contents of the PC.
  • Page 226 ® User Manual Rotate Left Syntax RL dst Instruction Format Address Mode Cycles (Hex) Operation C ← dst(7) dst(0) ← dst(7) dst(1) ← dst(0) dst(2) ← dst(1) dst(3) ← dst(2) dst(4) ← dst(3) dst(5) ← dst(4) dst(6) ← dst(5) dst(7) ← dst(6) The contents of the destination operand are rotated left by one bit position.
  • Page 227 ® User Manual of the operand. For example, if Working Register R12 (CH) is the destination operand, then is used as the destination operand in the Op Code. Example 1 If the contents of Register ), the statement: 10001000b RL C6h Op Code: 80 C6 leaves the value ) in Register...
  • Page 228 ® User Manual Rotate Left Through Carry Syntax RLC dst Instruction Format Address Mode Cycles (Hex) Operation C← dst(7) dst(0) ← C dst(1) ← dst(0) dst(2) ← dst(1) dst(3) ← dst(2) dst(4) ← dst(3) dst(5) ← dst(4) dst(6) ← dst(5) dst(7) ←...
  • Page 229 ® User Manual of the operand. For example, if Working Register R12 (CH) is the destination operand, then is used as the destination operand in the Op Code. Example 1 If the C Flag is reset and Register C6 contains ), the statement: 10001111b RLC C6...
  • Page 230 ® User Manual Rotate Right Syntax RR dst Instruction Format Address Mode Cycles (Hex) Operation C ← dst(0) dst(0) ← dst(1) dst(1) ← dst(2) dst(2) ← dst(3) dst(3) ← dst(4) dst(4) ← dst(5) dst(5) ← dst(6) dst(6) ← dst(7) dst(7) ← dst(0) The contents of the destination operand are rotated to the right by one bit position.
  • Page 231 ® User Manual Example 1 If the contents of Working Register R6 are (00110001B), the statement: RR R6 Op Code: E0 E6 leaves the value ) in Working Register R6. The C, V, and S Flags are set, 10011000 and the Z Flag is cleared. Example 2 If the contents of Register C6 are and the contents of Register...
  • Page 232 ® User Manual Rotate Right Through Carry Syntax RRC dst Instruction Format Address Mode Cycles (Hex) Operation C ← dst(0) dst(0) ← dst(1) dst(1) ← dst(2) dst(2) ← dst(3) dst(3) ← dst(4) dst(4) ← dst(5) dst(5) ← dst(6) dst(6) ← dst(7) dst(7) ←...
  • Page 233 ® User Manual of the operand. For example, if Working Register R12 (CH) is the destination operand, then is used as the destination operand in the Op Code. Example 1 If the contents of Register ) and the C Flag is reset, the state- 11011101b ment: RRC C6h...
  • Page 234 ® User Manual Set Carry Flag Syntax Instruction Format Cycles (Hex) Operation C ← 1 The C Flag is set to 1, regardless of its previous value. Flag Description Set to 1 Unaffected Unaffected Unaffected Unaffected Unaffected Example If the C Flag is currently reset, the statement: Op Code: DF sets the Carry Flag to 1.
  • Page 235 ® User Manual Set Register Pointer Syntax SRP src Instruction Format Address Mode Cycles (Hex) Operation RP ← src The specified value is loaded into the Register Pointer (RP) (Control Register ). Bits 7-4 determine the Working Register Group. Bits 3-0 selects the Expanded Register Bank. Addressing of un-implemented Working Register Group, while using Expanded Register Banks, points to Bank 0.
  • Page 236 ® User Manual Register Pointer (FDh) Expanded Register Contents (Hex) Bank (Hex) xxxx 1111 xxxx 1110 xxxx 1101 xxxx 1100 xxxx 1011 xxxx 1010 xxxx 1001 xxxx 1000 xxxx 0111 xxxx 0110 xxxx 0101 xxxx 0100 xxxx 0011 xxxx 0010 xxxx 0001 xxxx 0000 Flag...
  • Page 237 ® User Manual group of 16 registers. Registers can be accessed as Working Registers R0 to R15. Example 3 The statement: SRP 0Fh Op Code: 31 0F ← sets the Register Pointer to access Expanded Register Bank F, Reg to Reg , as the current Working Registers.
  • Page 238 ® User Manual Shift Right Arithmetic Syntax SRA dst Instruction Format Address Mode Cycles (Hex) Operation C ← dst(0) dst(0) ← dst(1) dst(1) ← dst(2) dst(2) ← dst(3) dst(3) ← dst(4) dst(4) ← dst(5) dst(5) ← dst(6) dst(6) ← dst(7) dst(7) ←...
  • Page 239 ® User Manual the operand. For example, if Working Register is the destination operand, then R12 (CH) is used as the destination operand in the Op Code. Example 1 If the contents of Working Register R6 are (00110001B), the statement: SRA R6 Op Code: D0 E6 leaves the value...
  • Page 240 ® User Manual STOP Syntax STOP Instruction Format Cycles (Hex) Operation This instruction turns OFF the internal system clock (SCLK) and external crystal (XTAL) oscillation, and reduces the standby current. STOP mode is terminated by a RESET which causes the processor to restart the application program at address 000Ch Flag Description...
  • Page 241 ® User Manual Subtract Syntax SUB dst, src Instruction Format Address Mode Cycles (Hex) Operation dst ← dst–src The source operand is subtracted from the destination operand and the result is stored in the destination operand. The contents of the source operand are not affected. Subtraction is performed by adding the two’s complement of the source operand to the destination oper- and.
  • Page 242 ® User Manual Example 1 If Working Register R3 contains , and Working Register R11 contains , the state- ment: SUB R3, R11 Op Code: 22 3B leaves the value F6h in Working Register R3. The C, S, and D Flags are set, and the Z, V, and H Flags are cleared.
  • Page 243 ® User Manual Example 6 If Register contains , Register contains , the statement: SUB @D4h, #02h Op Code: 17 D4 02 leaves the value in Register . The D Flag is set, and the C, Z, S, V, and H Flags are cleared.
  • Page 244 ® User Manual Subtract With Carry Syntax SBC dst, src Instruction Format Address Mode Cycles (Hex) Operation dst ← dst–src–C The source operand, along with the setting of the C Flag, is subtracted from the destination operand and the result is stored in the destination operand. The contents of the source operand are not affected.
  • Page 245 ® User Manual Example 1 If Working Register R3 contains , the C Flag is set to 1, and Working Register R11 contains , the statement: SBC R3, R11 Op Code: 32 3B leaves the value in Working Register R3. The C, S, and D Flags are set, and the Z, V, and H Flags are all cleared.
  • Page 246 ® User Manual leaves the value in Register . The D Flag is set, and the C, Z, S, V, and H Flags are cleared. Example 6 If Register contains , Register contains 4Ch, and the C Flag is set, the state- ment: SBC @D4h, #02h Op Code: 37 D4 02...
  • Page 247 ® User Manual Swap Nibbles Syntax SWAP dst Instruction Format Address Mode Cycles (Hex) Operation dst(7-4) ↔ dst(3-0) The contents of the lower four bits and upper four bits of the destination operand are swapped. Flag Description Unaffected Set if the result is zero; cleared otherwise. Set if the result bit 7 is set;...
  • Page 248 ® User Manual Example 2 If Working Register R5 contains and Register contains (10110011B), the statement: SWAP @R5h Op Code: F1 E5 leaves the value (00111011B) in Register . The Z and S Flags are cleared. UM001604-0108 Instruction Description...
  • Page 249 ® User Manual Test Complement Under Mask Syntax TCM dst, src Instruction Format Address Mode Cycles (Hex) dst src Operation (NOT dst) AND src This instruction tests selected bits in the destination operand for a logical 1 value. The bits to be tested are specified by setting a 1 bit in the corresponding bit position in the source operand (the mask).
  • Page 250 ® User Manual Example 1 If Working Register R3 contains ) and Working Register R7 contains the 01000101b value ) (bit 0 is being tested if it is 1), the statement: 00000001b TCM R3, R7 Op Code: 62 37 sets the Z Flag indicating bit 0 in the destination operand is 1. The V and S Flags are cleared.
  • Page 251 ® User Manual tests bit 1 of the destination operand for 1. The Z Flag is set indicating bit 1 in the destina- tion operand was 1. The S and V Flags are cleared. Example 6 If Register contains , and Register contains ), the state- 00001111b...
  • Page 252 ® User Manual Test Under Mask Syntax TM dst, src Instruction Format Address Mode Cycles (Hex) dst src Operation dst AND src This instruction tests selected bits in the destination operand for a 0 logical value. The bits to be tested are specified by setting a 1 bit in the corresponding bit position in the source operand (the mask).
  • Page 253 ® User Manual Example 1 If Working Register R3 contains ) and Working Register R7 contains the 01000101b value ) (bit 1 is being tested if it is 0), the statement: 00000010b TM R3, R7 Op Code: 72 37 sets the Z Flag indicating bit 1 in the destination operand is 0. The V and S Flags are cleared.
  • Page 254 ® User Manual tests bit 1 of the destination operand for 0. The Z Flag is set indicating bit 1 in the destina- tion operand was 0. The S and V Flags are cleared. Example 6 If Register contains , and Register contains ), the state- 00001111b...
  • Page 255 ® User Manual Watchdog Timer Syntax Instruction Format Cycles (Hex) Operation ® The WDT is a retriggerable one shot timer that resets Z8 CPU if it reaches its terminal count. The WDT is initially enabled by executing the WDT instruction. Each subsequent execution of the WDT instruction refreshes the timer and prevents the WDT from timing out.
  • Page 256 ® User Manual Watchdog Timer Enable During Halt Mode Syntax Instruction Format Cycles (Hex) Operation When this instruction is executed it enables the WDT during HALT mode. If this instruc- tion is not executed the WDT stops when entering HALT mode. This instruction does not clear the counter, it just makes it possible to have the WDT function running during HALT mode.

  • Page 257: Index

    ® User Manual Index Framing Errors 119 acknowledge 107 Address Strobe 136 Addressing 132 general-purpose 115 ART 115 general-purpose register 115 Bit Rate 116 HALT 110 Bit-Rate 116 HALT and STOP 110 Bus Operation 134 Halt Mode Operation 110 Bus Timing 137 by 16 112 Initialization 99 Input 115...
  • Page 258 ® User Manual IRQ Software Interrupt Generation 104 Recovery Register 112 Register File 104 Reset 109 Reset Conditions 109 RUN 110 Latency 107 RUN mode 110 Logic and Timing 98 SCON 123 Mask 101, 109 Serial 115 Master/Slave 123 Serial Input/Output 115 Master/Slave selection 123 Serial Peripheral Interface 122 Shift 118...
  • Page 259 ® User Manual Vectored 105 Worst Case 107 Vectored Interrupt Cycle Timing 107 Vectored Processing 105 Z8 140 Z8 Reset Conditions 140 UM001604-0108 Index...

  • Page 260: Customer Support

    Customer Support For answers to technical questions about the product, documentation, or any other issues with Zilog’s offerings, please visit Zilog’s Knowledge Base at http://www.zilog.com/kb. For any comments, detail technical questions, or reporting problems, please visit Zilog’s Technical Support at http://support.zilog.com.
  • Page 261 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: ZiLOG Z86E3412SEG...

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