Coding Multiple Right-Hand Instructions; Branching Instruction Lines - Omron CPM1 Programming Manual

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Coding Multiple Right-hand Instructions

00000 00003
00001
00002
HR 0000
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Branching Instruction Lines

Branching
point
00000
Diagram A: Correct Operation
Branching
point
00000
Diagram B: Incorrect Operation
If there is more than one right-hand instruction executed with the same execu-
tion condition, they are coded consecutively following the last condition on the
instruction line. In the following example, the last instruction line contains one
more condition that corresponds to an AND with IR 00004.
00004
When an instruction line branches into two or more lines, it is sometimes neces-
sary to use either interlocks or TR bits to maintain the execution condition that
existed at a branching point. This is because instruction lines are executed
across to a right-hand instruction before returning to the branching point to
execute instructions one a branch line. If a condition exists on any of the instruc-
tion lines after the branching point, the execution condition could change during
this time making proper execution impossible. The following diagrams illustrate
this. In both diagrams, instruction 1 is executed before returning to the branching
point and moving on to the branch line leading to instruction 2.
00002
00001
00002
If, as shown in diagram A, the execution condition that existed at the branching
point cannot be changed before returning to the branch line (instructions at the
far right do not change the execution condition), then the branch line will be
executed correctly and no special programming measure is required.
If, as shown in diagram B, a condition exists between the branching point and the
last instruction on the top instruction line, the execution condition at the branch-
ing point and the execution condition after completing the top instruction line will
sometimes be different, making it impossible to ensure correct execution of the
branch line.
There are two means of programming branching programs to preserve the
execution condition. One is to use TR bits; the other, to use interlocks
(IL(02)/IL(03)).
Address Instruction
HR 0001
00000
00001
20000
00002
00003
00004
20001
00005
00006
00007
00008
Address
Instruction 1
00000
00001
Instruction 2
00002
00003
Instruction 1
Address
00000
Instruction 2
00001
00002
00003
00004
Section
Operands
LD 00000
OR 00001
OR 00002
OR HR 0000
AND 00003
OUT HR 0001
OUT 20000
AND 00004
OUT 20001
Instruction Operands
LD 00000
Instruction 1
AND 00002
Instruction 2
Instruction Operands
LD 00000
AND 00001
Instruction 1
AND 00002
Instruction 2
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